Inventor
HETZEL ASMUS
DE27 patents
⚠️ This page may combine multiple inventors who share the name “HETZEL ASMUS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
CADENCE DESIGN SYSTEMS INC
22 patentsUS7398503B2Jul 8, 2008
Method and apparatus for pre-tabulating sub-networks
CADENCE DESIGN SYSTEMS INC14 citations92
US7197738B1Mar 27, 2007
Method and apparatus for routing
CADENCE DESIGN SYSTEMS INC42 citations92
US7441220B2Oct 21, 2008
Local preferred direction architecture, tools, and apparatus
CADENCE DESIGN SYSTEMS INC18 citations90
US7340711B2Mar 4, 2008
Method and apparatus for local preferred direction routing
CADENCE DESIGN SYSTEMS INC24 citations88
US7721243B2May 18, 2010
Method and apparatus for routing
CADENCE DESIGN SYSTEMS INC13 citations84
US7543251B2Jun 2, 2009
Method and apparatus replacing sub-networks within an IC design
CADENCE DESIGN SYSTEMS INC9 citations84
US7472366B1Dec 30, 2008
Method and apparatus for performing a path search
CADENCE DESIGN SYSTEMS INC10 citations84
US7412682B2Aug 12, 2008
Local preferred direction routing
CADENCE DESIGN SYSTEMS INC15 citations84
US7024639B2Apr 4, 2006
Method and apparatus for specifying encoded sub-networks
CADENCE DESIGN SYSTEMS INC14 citations84
US6854097B2Feb 8, 2005
Method and apparatus for performing technology mapping
CADENCE DESIGN SYSTEMS INC13 citations84
US8010929B2Aug 30, 2011
Method and apparatus for generating layout regions with local preferred directions
CADENCE DESIGN SYSTEMS INC13 citations83
US6857117B2Feb 15, 2005
Method and apparatus for producing a circuit description of a design
CADENCE DESIGN SYSTEMS INC10 citations82
US7801325B1Sep 21, 2010
Watermarking a chip design based on frequency of geometric structures
CADENCE DESIGN SYSTEMS INC15 citations77
US7100143B2Aug 29, 2006
Method and apparatus for pre-tabulating sub-networks
CADENCE DESIGN SYSTEMS INC8 citations74
US7076760B2Jul 11, 2006
Method and apparatus for specifying encoded sub-networks
CADENCE DESIGN SYSTEMS INC10 citations74
US6990650B2Jan 24, 2006
Method and apparatus for performing technology mapping
CADENCE DESIGN SYSTEMS INC10 citations74
US6954910B2Oct 11, 2005
Method and apparatus for producing a circuit description of a design
CADENCE DESIGN SYSTEMS INC8 citations74
US6848086B2Jan 25, 2005
Method and apparatus for performing technology mapping
CADENCE DESIGN SYSTEMS INC11 citations74
US7594196B2Sep 22, 2009
Block interstitching using local preferred direction architectures, tools, and apparatus
CADENCE DESIGN SYSTEMS INC5 citations63
US7383524B2Jun 3, 2008
Structure for storing a plurality of sub-networks
CADENCE DESIGN SYSTEMS INC4 citations63
US6854098B2Feb 8, 2005
Method and apparatus for performing technology mapping
CADENCE DESIGN SYSTEMS INC5 citations63
US7707537B2Apr 27, 2010
Method and apparatus for generating layout regions with local preferred directions
CADENCE DESIGN SYSTEMS INC4 citations62