Inventor

SHERLEKAR DEEPAK D

US23 patents

⚠️ This page may combine multiple inventors who share the name “SHERLEKAR DEEPAK D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHERLEKAR DEEPAK D

SYNOPSYS INC

FinFET cell architecture with insulator structure

FinFET cell architecture with power traces

FinFET cell architecture with power traces

N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch

FinFET cell architecture with power traces

N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch

Power routing in standard cells

FinFET cell architecture with insulator structure

Retention flip-flop circuits for low power applications

On-the-fly multi-bit flip flop generation

On-the-fly multi-bit flip flop generation

Power efficient retention flip flop circuit

SHERLEKAR DEEPAK D

Power routing in standard cell designs

Power routing in standard cells

Pin routing in standard cells

Cell architecture for increasing transistor size

Various methods and apparatuses to route multiple power rails to a cell

VIRAGE LOGIC CORP

Gate array architecture using elevated metal levels for customization

Various methods and apparatuses to preserve a logic state for a volatile latch circuit

Various methods and apparatuses to route multiple power rails to a cell

Various methods and apparatuses to preserve a logic state for a volatile latch circuit

MOROZ VICTOR

N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch

IBM

Method and system for removing hardware design overlap