Inventor

SIAU CHANG HUA

US68 patents

⚠️ This page may combine multiple inventors who share the name “SIAU CHANG HUA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SIAU CHANG HUA

UNITY SEMICONDUCTOR CORP

Low read current architecture for memory

Sensing a signal in a two-terminal memory array having leakage current

Two-cycle sensing in a two-terminal memory array having leakage current

Circuits and techniques to compensate data signals for variations of parameters affecting memory cells in cross-point arrays

High voltage switching circuitry for a cross-point array

High voltage switching circuitry for a cross-point array

Contemporaneous margin verification and memory access for memory cells in cross point memory arrays

Method for sensing a signal in a two-terminal memory array having leakage current

Method for two-cycle sensing in a two-terminal memory array having leakage current

Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations

Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations

Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations

Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory

Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory

High voltage switching circuitry for a cross-point array

Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory

Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations

Array voltage regulating technique to enable data operations on large memory arrays with resistive memory elements

Access signal adjustment circuits and methods for memory cells in a cross-point array

Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory

Access signal adjustment circuits and methods for memory cells in a cross-point array

Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory

High voltage switching circuitry for a cross-point array

Access signal adjustment circuits and methods for memory cells in a cross-point array

Array voltage regulating technique to enable data operations on large cross-point memory arrays with resistive memory elements

Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory

High voltage switching circuitry for a cross-point array

Circuits and techniques to compensate data signals for variations of parameters affecting memory cells in cross point arrays

Access signal adjustment circuits and methods for memory cells in a cross-point array

Array voltage regulating technique to enable data operations on large memory arrays with resistive memory elements

Array voltage regulating technique to enable data operations on large memory arrays with resistive memory elements

Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations

Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations

Local bit lines and methods of selecting the same to access memory elements in cross-point arrays

Array voltage regulating technique to enable data operations on large memory arrays with resistive memory elements

Access signal adjustment circuits and methods for memory cells in a cross-point array

High voltage switching circuitry for a cross-point array

Access signal conditioning for memory cells in an array

High voltage switching circuitry for a cross-point array

SIAU CHANG HUA

Array voltage regulating technique to enable data operations on large cross-point memory arrays with resistive memory elements

Local bit lines and methods of selecting the same to access memory elements in cross-point arrays

Multilayer cross-point memory array having reduced disturb susceptibility

Memory array with local bitlines and local-to-global bitline pass gates and gain stages

Signal margin improvement for read operations in a cross-point memory array

Local bit lines and methods of selecting the same to access memory elements in cross-point arrays

CHEVALLIER CHRISTOPHE

Access signal adjustment circuits and methods for memory cells in a cross-point array

Memory architectures and techniques to enhance throughput for cross-point arrays

Access signal adjustment circuits and methods for memory cells in a cross-point array

CHEVALLIER CHRISTOPHE J

Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory

BATEMAN BRUCE

Low read current architecture for memory