Inventor
BHANDARU MALINI K
US21 patents
⚠️ This page may combine multiple inventors who share the name “BHANDARU MALINI K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
14 patentsUS10191532B2Jan 29, 2019
Configuring power management functionality in a processor
INTEL CORP3 citations84
US11507643B2Nov 22, 2022
Licensing in the cloud
INTEL CORP3 citations71
US10289814B2May 14, 2019
Licensing in the cloud
INTEL CORP1 citations71
US9141426B2Sep 22, 2015
Processor having per core and package level P0 determination functionality
INTEL CORP6 citations70
US11237614B2Feb 1, 2022
Multicore processor with a control register storing an indicator that two or more cores are to operate at independent performance states
INTEL CORP0 citations62
US9760155B2Sep 12, 2017
Configuring power management functionality in a processor
INTEL CORP1 citations62
US9235244B2Jan 12, 2016
Configuring power management functionality in a processor
INTEL CORP1 citations62
US11775621B2Oct 3, 2023
Licensing in the cloud
INTEL CORP0 citations61
US10554574B2Feb 4, 2020
Resource management techniques for heterogeneous resource clouds
INTEL CORP1 citations61
US9384076B2Jul 5, 2016
Allocating machine check architecture banks
INTEL CORP2 citations60
US10877549B2Dec 29, 2020
Configuring power management functionality in a processor
INTEL CORP0 citations52
US10203741B2Feb 12, 2019
Configuring power management functionality in a processor
INTEL CORP0 citations52
US11200210B2Dec 14, 2021
Method of efficient backup of distributed file system files with transparent data access
INTEL CORP0 citations41
US11520700B2Dec 6, 2022
Techniques to support a holistic view of cache class of service for a processor cache
INTEL CORP0 citations40
BHANDARU MALINI K
5 patentsUS8984313B2Mar 17, 2015
Configuring power management functionality in a processor including a plurality of cores by utilizing a register to store a power domain indicator
BHANDARU MALINI K18 citations92
US9436245B2Sep 6, 2016
Dynamically computing an electrical design point (EDP) for a multicore processor
BHANDARU MALINI K16 citations83
US9354689B2May 31, 2016
Providing energy efficient turbo operation of a processor
BHANDARU MALINI K10 citations83
US9323316B2Apr 26, 2016
Dynamically controlling interconnect frequency in a processor
BHANDARU MALINI K8 citations80
US9436254B2Sep 6, 2016
Method and apparatus for per core performance states
BHANDARU MALINI K0 citations50