Inventor
BRAHMADATHAN SANDEEP
IN22 patents
⚠️ This page may combine multiple inventors who share the name “BRAHMADATHAN SANDEEP”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
AMPERE COMPUTING LLC
10 patentsUS12204410B2Jan 21, 2025
Integrated error correction code (ECC) and parity protection in memory control circuits for increased memory utilization
AMPERE COMPUTING LLC14 citations85
US12019565B2Jun 25, 2024
Advanced initialization bus (AIB)
AMPERE COMPUTING LLC4 citations68
US11481270B1Oct 25, 2022
Method and system for sequencing data checks in a packet
AMPERE COMPUTING LLC2 citations65
US12314130B2May 27, 2025
Parity protected memory blocks merged with error correction code (ECC) protected blocks in a codeword for increased memory utilization
AMPERE COMPUTING LLC0 citations61
US11934263B2Mar 19, 2024
Parity protected memory blocks merged with error correction code (ECC) protected blocks in a codeword for increased memory utilization
AMPERE COMPUTING LLC1 citations61
US12411778B2Sep 9, 2025
Advanced initialization bus (AIB)
AMPERE COMPUTING LLC0 citations56
US11868209B2Jan 9, 2024
Method and system for sequencing data checks in a packet
AMPERE COMPUTING LLC0 citations55
US12159056B2Dec 3, 2024
Extending functionality of memory controllers in a processor-based device
AMPERE COMPUTING LLC0 citations51
US12451206B2Oct 21, 2025
Extending functionality of memory controllers using a loopback mode for testing in a processor-based device
AMPERE COMPUTING LLC0 citations45
US12282064B2Apr 22, 2025
Component die validation built-in self-test (VBIST) engine
AMPERE COMPUTING LLC0 citations43
CADENCE DESIGN SYSTEMS INC
9 patentsUS9811273B1Nov 7, 2017
System and method for reliable high-speed data transfer in multiple data rate nonvolatile memory
CADENCE DESIGN SYSTEMS INC47 citations93
US9886987B1Feb 6, 2018
System and method for data-mask training in non-provisioned random access memory
CADENCE DESIGN SYSTEMS INC21 citations90
US8812898B1Aug 19, 2014
System and method for transfer of data between memory with dynamic error recovery
CADENCE DESIGN SYSTEMS INC26 citations88
US9159423B1Oct 13, 2015
Robust erase page detection logic for NAND flash memory devices
CADENCE DESIGN SYSTEMS INC22 citations86
US10545866B1Jan 28, 2020
Method and system for efficient re-determination of a data valid window
CADENCE DESIGN SYSTEMS INC10 citations81
US8880980B1Nov 4, 2014
System and method for expeditious transfer of data from source to destination in error corrected manner
CADENCE DESIGN SYSTEMS INC14 citations78
US9471094B1Oct 18, 2016
Method of aligning timing of a chip select signal with a cycle of a memory device
CADENCE DESIGN SYSTEMS INC11 citations76
US7941587B2May 10, 2011
Programmable sequence generator for a flash memory controller
CADENCE DESIGN SYSTEMS INC4 citations60
US10885952B1Jan 5, 2021
Memory data transfer and switching sequence
CADENCE DESIGN SYSTEMS INC0 citations46