Inventor
ITO FUMITOSHI
JP39 patents
⚠️ This page may combine multiple inventors who share the name “ITO FUMITOSHI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
CANON KK
9 patentsUS7730490B2Jun 1, 2010
System with user access-control information having signature and flow setting information for controlling order of performance of functions
CANON KK17 citations84
US7639836B2Dec 29, 2009
Image copying device and image processing system
CANON KK13 citations84
US10445477B2Oct 15, 2019
Information processing system, method of controlling the system, information processing apparatus, web server, and storage medium
CANON KK3 citations73
US9842199B2Dec 12, 2017
Information processing system, method of controlling the system, information processing apparatus, web server, and storage medium
CANON KK2 citations73
US9648200B2May 9, 2017
Image processing system storing received image data in folder, image processing method, and storage medium
CANON KK2 citations71
US10051154B2Aug 14, 2018
Information processing apparatus, control method in information processing apparatus, and image processing apparatus
CANON KK1 citations52
US9141990B2Sep 22, 2015
Expense registration system for registering expenses related to document received by fax
CANON KK0 citations52
US10701225B2Jun 30, 2020
User interface definition for information processing apparatus, control method, and storage medium
CANON KK0 citations42
US9635214B2Apr 25, 2017
Image processing system for setting filename to received image data, image processing method therefor, and storage medium
CANON KK0 citations40
SANDISK CORP
8 patentsUS7768826B2Aug 3, 2010
Methods for partitioned erase and erase verification in non-volatile memory to compensate for capacitive coupling effects
SANDISK CORP26 citations92
US7535766B2May 19, 2009
Systems for partitioned soft programming in non-volatile memory
SANDISK CORP39 citations92
US7499317B2Mar 3, 2009
System for partitioned erase and erase verification in a non-volatile memory to compensate for capacitive coupling
SANDISK CORP30 citations92
US7499338B2Mar 3, 2009
Partitioned soft programming in non-volatile memory
SANDISK CORP50 citations92
US7495954B2Feb 24, 2009
Method for partitioned erase and erase verification to compensate for capacitive coupling effects in non-volatile memory
SANDISK CORP39 citations92
US7440326B2Oct 21, 2008
Programming non-volatile memory with improved boosting
SANDISK CORP38 citations92
US7977186B2Jul 12, 2011
Providing local boosting control implant for non-volatile memory
SANDISK CORP4 citations63
US7705387B2Apr 27, 2010
Non-volatile memory with local boosting control implant
SANDISK CORP6 citations63
ITO FUMITOSHI
7 patentsUS8400658B2Mar 19, 2013
Network device and workflow processing system
ITO FUMITOSHI11 citations83
US8947699B2Feb 3, 2015
Image processing apparatus and control method thereof
ITO FUMITOSHI6 citations72
US9148529B2Sep 29, 2015
Information processing apparatus, web server, control method and storage medium
ITO FUMITOSHI3 citations62
US8699052B2Apr 15, 2014
Image forming apparatus, control method, and program
ITO FUMITOSHI3 citations62
US8593665B2Nov 26, 2013
Image forming system and information processing apparatus
ITO FUMITOSHI2 citations62
US8493586B2Jul 23, 2013
Work flow system for deciding whether to execute the work flow based on function restriction information
ITO FUMITOSHI1 citations51
US8576634B2Nov 5, 2013
Semiconductor device comprising a memory cell group having a gate width larger than a second memory cell group
ITO FUMITOSHI0 citations50
SANDISK TECHNOLOGIES INC
6 patentsUS8885416B2Nov 11, 2014
Bit line current trip point modulation for reading nonvolatile storage elements
SANDISK TECHNOLOGIES INC13 citations84
US8026544B2Sep 27, 2011
Fabricating and operating a memory array having a multi-level cell region and a single-level cell region
SANDISK TECHNOLOGIES INC12 citations84
US8988947B2Mar 24, 2015
Back bias during program verify of non-volatile storage
SANDISK TECHNOLOGIES INC5 citations73
US8942047B2Jan 27, 2015
Bit line current trip point modulation for reading nonvolatile storage elements
SANDISK TECHNOLOGIES INC4 citations73
US8503244B2Aug 6, 2013
Fabricating and operating a memory array having a multi-level cell region and a single-level cell region
SANDISK TECHNOLOGIES INC2 citations63
US8354322B2Jan 15, 2013
Fabricating and operating a memory array having a multi-level cell region and a single-level cell region
SANDISK TECHNOLOGIES INC2 citations63
RENESAS TECH CORP
5 patentsUS7087955B2Aug 8, 2006
Semiconductor device and a method of manufacturing the same
RENESAS TECH CORP27 citations92
US6734114B2May 11, 2004
Method for manufacturing semiconductor integrated circuit device
RENESAS TECH CORP10 citations73
US7349250B2Mar 25, 2008
Semiconductor device
RENESAS TECH CORP7 citations72
US7719052B2May 18, 2010
Semiconductor device
RENESAS TECH CORP1 citations61
US7067889B2Jun 27, 2006
Method for manufacturing semiconductor integrated circuit device
RENESAS TECH CORP0 citations52