Inventor

BORKOVIC DRAZEN

US41 patents

⚠️ This page may combine multiple inventors who share the name “BORKOVIC DRAZEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BORKOVIC DRAZEN

AMAZON TECH INC

DMA synchronization using alternating semaphores

Allocation and placement of resources for network computation

Static memory allocation for neural network inference

Time-based memory allocation for neural network inference

Performance debug for networks

Saving intermediate outputs of a neural network

Breakpoints in neural network accelerator

Low latency neural network model loading

Reconfigurable neural network processing based on subgraph recognition

Compile-time scheduling

Synchronization of computation engines with non-blocking instructions

Using vector clocks to simplify a dependency graph in a neural network accelerator

Configurable delay insertion in compiled instructions

Efficient utilization of processing element array

Efficient race-condition detection

Synchronization of DMA transfers for large number of queues

Synchronization of concurrent computation engines

Synchronization of concurrent computation engines

Neural network operation reordering for parallel execution

Synchronization of concurrent computation engines

Fast context switching for computational networks

Breakpoints in neural network accelerator

Efficient utilization of processing element array

Vector clocks for highly concurrent execution engines

Vector clocks for highly concurrent execution engines

Neural network operation reordering for parallel execution

Event assignment for synchronization of concurrent execution engines

Reconfigurable neural network processing based on subgraph recognition

Neural network layer-by-layer debugging

Hierarchical partitioning of operators

SYNPLICITY INC

Method and apparatus for circuit partitioning and trace assignment in circuit design

Reducing clock skew in clock gating circuits

Method and apparatus for the design and analysis of digital circuits with time division multiplexing

Reducing clock skew in clock gating circuits

SYNOPSYS INC

Circuit partitioning and trace assignment in circuit design

Method and apparatus for circuit partitioning and trace assignment in circuit design

Analysis of digital circuits with time division multiplexing

PANDEY AWARTIKA

Method and apparatus for circuit partitioning and trace assignment in circuit design

Circuit partitioning and trace assignment in circuit design

QUICKLOGIC CORP

Programmable device with an embedded portion for receiving a standard circuit design

BORKOVIC DRAZEN

Method and apparatus for the design and analysis of digital circuits with time division multiplexing