Inventor

SHAO DONGBING

US65 patents

⚠️ This page may combine multiple inventors who share the name “SHAO DONGBING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHAO DONGBING

IBM

Predicting local layout effects in circuit design patterns

Generation of hotspot-containing physical design layout patterns

Classification and localization of hotspots in integrated physical design layouts

Nanosheet capacitor

Air gap electrostatic discharge structure for high speed circuits

Self-aligned double patterning with spacer-merge region

Tight pitch via structures enabled by orthogonal and non-orthogonal merged vias

Semiconductor process modeling to enable skip via in place and route flow

Semiconductor fabrication design rule loophole checking for design for manufacturability optimization

Circuit wiring techniques for stacked transistor structures

Wirebond cross-talk reduction for quantum computing chips

Horizontal-trench capacitor

Bump connection placement in quantum devices in a flip chip configuration

Perpendicular stacked field-effect transistor device

Detecting hotspots in physical design layout patterns utilizing hotspot detection model with data augmentation

Superconducting quantum circuits layout design verification

Automatic design flow from schematic to layout for superconducting multi-qubit systems

Semiconductor fabrication design rule loophole checking for design for manufacturability optimization

Air gap metal tip electrostatic discharge protection

Air gap metal tip electrostatic discharge protection

Semiconductor fabrication design rule loophole checking for design for manufacturability optimization

Integrated circuit design layout optimizer based on process variation and failure mechanism

Nanosheet capacitor

Optimizing integrated circuit designs based on interactions between multiple integration design rules

Circuit wiring techniques for stacked transistor structures

Bump connection placement in quantum devices in a flip chip configuration

Wirebond cross-talk reduction for quantum computing chips

Semiconductor process modeling to enable skip via in place and route flow

Via design optimization to improve via resistance

Nanosheet capacitor

Reducing the impact of charged particle beams in critical dimension analysis

Self-aligned double patterning with spacer-merge region

Addressing layout retargeting shortfalls

Highway jumper to enable long range connectivity for superconducting quantum computer chip

Coupled-line bus to suppress classical crosstalk for superconducting qubits

Qubit frequency tuning structures and fabrication methods for flip chip quantum computing devices

Qubit frequency tuning structures and fabrication methods for flip chip quantum computing devices

Hybrid readout package for quantum multichip bonding

Air gap metal tip electrostatic discharge protection

Air gap metal tip electrostatic discharge protection

Qubit frequency tuning structures and fabrication methods for flip chip quantum computing devices

Incorporation of process variation contours in design rule and risk estimation aspects of design for manufacturability to increase fabrication yield

Multipole filter on a quantum device with multiplexing and signal separation

TESSERA LLC

Two-color self-aligned double patterning (SADP) to yield static random access memory (SRAM) and dense logic

Two-color self-aligned double patterning (SADP) to yield static random access memory (SRAM) and dense logic

BAILEY TODD C

Pattern recognition with edge correction for design based metrology

Pattern recognition with edge correction for design based metrology

GLOBALFOUNDRIES INC

Integrated circuit line ends formed using additive processing

ADEIA SEMICONDUCTOR SOLUTIONS LLC

Two-color self-aligned double patterning (SADP) to yield static random access memory (SRAM) and dense logic

TESSERA INC

Two-color self-aligned double patterning (SADP) to yield static random access memory (SRAM) and dense logic