Inventor
CHINTHAKINDI ANIL KUMAR
US8 patents
Patents
8 patentsUS7361950B2Apr 22, 2008
Integration of a MIM capacitor with a plate formed in a well region and with a high-k dielectric
IBM17 citations91
US7763954B2Jul 27, 2010
Post last wiring level inductor using patterned plate process
IBM7 citations73
US7741698B2Jun 22, 2010
Post last wiring level inductor using patterned plate process
IBM6 citations73
US7573117B2Aug 11, 2009
Post last wiring level inductor using patterned plate process
IBM7 citations73
US7915134B2Mar 29, 2011
Method of integration of a MIM capacitor with a lower plate of metal gate material formed on an STI region or a silicide region formed in or on the surface of a doped well with a high K dielectric material
IBM6 citations72
US7732294B2Jun 8, 2010
Post last wiring level inductor using patterned plate process
IBM2 citations62
US7713792B2May 11, 2010
Fuse structure including monocrystalline semiconductor material layer and gap
IBM5 citations62
US7732295B2Jun 8, 2010
Post last wiring level inductor using patterned plate process
IBM0 citations51