Inventor
COOLBAUGH DOUGLAS DUANE
US26 patents
⚠️ This page may combine multiple inventors who share the name “COOLBAUGH DOUGLAS DUANE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
23 patentsUS6271100B1Aug 7, 2001
Chemically enhanced anneal for removing trench stress resulting in improved bipolar yield
IBM91 citations97
US6426265B1Jul 30, 2002
Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology
IBM25 citations92
US7361950B2Apr 22, 2008
Integration of a MIM capacitor with a plate formed in a well region and with a high-k dielectric
IBM17 citations91
US6936509B2Aug 30, 2005
STI pull-down to control SiGe facet growth
IBM16 citations89
US6255185B1Jul 3, 2001
Two step anneal for controlling resistor tolerance
IBM22 citations86
US6440811B1Aug 27, 2002
Method of fabricating a poly-poly capacitor with a SiGe BiCMOS integration scheme
IBM15 citations83
US7763954B2Jul 27, 2010
Post last wiring level inductor using patterned plate process
IBM7 citations73
US7741698B2Jun 22, 2010
Post last wiring level inductor using patterned plate process
IBM6 citations73
US7573117B2Aug 11, 2009
Post last wiring level inductor using patterned plate process
IBM7 citations73
US7915134B2Mar 29, 2011
Method of integration of a MIM capacitor with a lower plate of metal gate material formed on an STI region or a silicide region formed in or on the surface of a doped well with a high K dielectric material
IBM6 citations72
US6800921B1Oct 5, 2004
Method of fabricating a polysilicon capacitor utilizing fet and bipolar base polysilicon layers
IBM9 citations72
US6670228B2Dec 30, 2003
Method of fabricating a polysilicon capacitor utilizing FET and bipolar base polysilicon layers
IBM7 citations72
US7335927B2Feb 26, 2008
Lateral silicided diodes
IBM6 citations70
US6218315B1Apr 17, 2001
HTO (high temperature oxide) deposition for capacitor dielectrics
IBM13 citations68
US7732294B2Jun 8, 2010
Post last wiring level inductor using patterned plate process
IBM2 citations62
US7713829B2May 11, 2010
Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology
IBM1 citations62
US7214593B2May 8, 2007
Passivation for improved bipolar yield
IBM3 citations59
US6420747B2Jul 16, 2002
MOSCAP design for improved reliability
IBM3 citations57
US7732295B2Jun 8, 2010
Post last wiring level inductor using patterned plate process
IBM0 citations51
US7488643B2Feb 10, 2009
MIM capacitor and method of making same
IBM1 citations51
US7173274B2Feb 6, 2007
Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology
IBM0 citations51
US7381997B2Jun 3, 2008
Lateral silicided diodes
IBM0 citations49
US6674102B2Jan 6, 2004
Sti pull-down to control SiGe facet growth
IBM1 citations48