Inventor

MOROZ VICTOR

US151 patents

⚠️ This page may combine multiple inventors who share the name “MOROZ VICTOR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MOROZ VICTOR

SYNOPSYS INC

Methods of designing an integrated circuit on corrugated substrate

Integrated circuit on corrugated substrate

Method of IC production using corrugated substrate

Segmented channel MOS transistor

Integrated circuit on corrugated substrate

Method and apparatus for generating a layout for a transistor

Managing integrated circuit stress using dummy diffusion regions

One-time programmable memory using rupturing of gate insulation

Cells having transistors and interconnects including nanowires or 2D material strips

SRAM layouts

Managing integrated circuit stress using dummy diffusion regions

Method and apparatus for placing an integrated circuit device within an integrated circuit layout

Stress-managed revision of integrated circuit layouts

Method of correlating silicon stress to device instance parameters for circuit simulation

Parameter extraction of DFT

FinFET cell architecture with insulator structure

FinFET cell architecture with power traces

Stress-enhanced performance of a FinFet using surface/channel orientations and strained capping layers

Method and apparatus for placing transistors in proximity to through-silicon vias

Memory cells including vertical nanowire transistors

Memory cell including vertical transistors and horizontal nanowire bit lines

Nanowire or 2D material strips interconnects in an integrated circuit cell

FinFET cell architecture with power traces

Methods for fabricating high-density integrated circuit devices

Array with intercell conductors including nanowires or 2D material strips

Nanowire or 2D material strips interconnects in an integrated circuit cell

N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch

FinFET cell architecture with power traces

N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch

Managing integrated circuit stress using stress adjustment trenches

Simulation scaling with DFT and non-DFT

Parameter extraction of DFT

Simulation scaling with DFT and non-DFT

Iterative simulation with DFT and non-DFT

Method and apparatus for floating or applying voltage to a well of an integrated circuit

Methods for manufacturing integrated circuit devices having features with reduced edge curvature

Methods for manufacturing integrated circuit devices having features with reduced edge curvature

Method and apparatus for performing stress modeling of integrated circuit material undergoing material conversion

Pre-silicon design rule evaluation

MOROZ VICTOR

Analysis of stress impact on transistor performance

N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch

N-channel and P-channel end-to-end finfet cell architecture

Stress-managed revision of integrated circuit layouts

Integrated circuit devices having features with reduced edge curvature and methods for manufacturing the same

Methods for manufacturing integrated circuit devices having features with reduced edge curvature

KAWA JAMIL

N-channel and p-channel finFET cell architecture

N-channel and P-channel finFET cell architecture with inter-block insulator

APPLIED MATERIALS INC

Methods for forming a transistor

LIN XI-WEI

Method of correlating silicon stress to device instance parameters for circuit simulation

KING TSU-JAE

Integrated circuit on corrugated substrate