Inventor

QI YI

US54 patents

⚠️ This page may combine multiple inventors who share the name “QI YI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

QI YI

GLOBALFOUNDRIES INC

Method of forming vertical field effect transistors with different gate lengths and a resulting structure

Vertical field effect transistor formation with critical dimension control

Forming long channel FinFET with short channel vertical FinFET and related integrated circuit

Asymmetric spacer for preventing epitaxial merge between adjacent devices of a semiconductor and related method

Metal-insulator-metal capacitors with enlarged contact areas

Multiple Fin heights with dielectric isolation

Methods of forming EPI semiconductor material on the source/drain regions of a FinFET device

Methods of removing portions of fins by preforming a selectively etchable material in the substrate

Dual-strained nanowire and FinFET devices with dielectric isolation

Methods of forming 3D devices with dielectric isolation and a strained channel region

Methods of forming alternative material fins with reduced defect density for a FinFET semiconductor device

Metal-insulator-metal capacitors with dielectric inner spacers

Wrap-all-around contact for nanosheet-FET and method of forming same

Transistors with H-shaped or U-shaped channels and method for forming the same

Integrated circuit structure incorporating non-planar field effect transistors with different channel region heights and method

Vertical-transport field-effect transistors with an etched-through source/drain cavity

Raised fin structures and methods of fabrication

Raised fin structures and methods of fabrication

Forming alternative material fins with reduced defect density by performing an implantation/anneal defect generation process

FinFET device including a uniform silicon alloy fin

Faceted epitaxial source/drain regions

Multiple gate length device with self-aligned top junction

Method of forming a vertical field effect transistor (VFET) and a VFET structure

Boundary spacer structure and integration

Vertical-transport field-effect transistors with an etched-through source/drain cavity

Method of forming step doping channel profile for super steep retrograde well field effect transistor and resulting device

Dual-curvature cavity for epitaxial semiconductor growth

Repaired mask structures and resultant underlying patterned structures

Methods of forming epi semiconductor material on a thinned fin in the source/drain regions of a FinFET device

FinFET device with a wrap-around silicide source/drain contact structure

Field-effect transistors with a grown silicon-germanium channel

Fin-type transistors with spacers on the gates

Field-effect transistors with improved dielectric gap fill

Blanket EPI super steep retrograde well formation without Si recess

Transistor device structures with retrograde wells in CMOS applications

Single-curvature cavity for semiconductor epitaxy

Methods of forming transistors with retrograde wells in CMOS applications and the resulting device structures

Methods of forming transistors with retrograde wells in CMOS applications and the resulting device structures

Method of forming step doping channel profile for super steep retrograde well field effect transistor and resulting device

IBM

Monitoring interesting subjects

Vehicle position indexing

Parallelization of data processing

Transistor channel having vertically stacked nanosheets coupled by fin-shaped bridge regions

Transistor channel having vertically stacked nanosheets coupled by fin-shaped bridge regions

Parallelization of data processing

Monitoring interesting subjects

MCALPINE MICHAEL C

Method of manufacturing flexible piezoelectric structures

HUANG SHENG

Method and apparatus for programming assistance

KANG LAEGU

Blanket EPI super steep retrograde well formation without Si recess

NAT UNIV SINGAPORE

Cascaded, self-calibrated, single-pixel infrared hadamard transform spectrometer