Inventor

CHANG MU-TIEN

US57 patents

⚠️ This page may combine multiple inventors who share the name “CHANG MU-TIEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHANG MU-TIEN

SAMSUNG ELECTRONICS CO LTD

DRAM assist error correction mechanism for DDR SDRAM interface

3-D stacked memory with reconfigurable compute logic

DRAM assist error correction mechanism for DDR SDRAM interface

ISA extension for high-bandwidth memory

Techniques to reduce read-modify-write overhead in hybrid DRAM/NAND memory

Coordinated near-far memory controller for process-in-HBM

Method to deliver in-DRAM ECC information through DDR bus

Tail response time reduction method for SSD

Hybrid memory controller for arbitrating access to volatile and non-volatile memories in a hybrid memory group

Optimized hopscotch multiple hash tables for efficient memory in-line deduplication application

HBM with in-memory cache manager

DRAM assist error correction mechanism for DDR SDRAM interface

ISA extension for high-bandwidth memory

Systems and methods for write and flush support in hybrid memory

DRAM assist error correction mechanism for DDR SDRAM interface

Method to deliver in-DRAM ECC information through DDR bus

Method to deliver in-DRAM ECC information through DDR bus

Coordinated in-module RAS features for synchronous DDR compatible memory

Self-optimized power management for DDR-compatible memory systems

Mitigating DRAM cache metadata access overhead with SRAM metadata cache and bloom filter

Methods for addressing high capacity SDRAM-like memory without increasing pin cost

Virtual bucket multiple hash tables for efficient memory in-line deduplication application

Bandwidth boosted stacked memory

ISA extension for high-bandwidth memory

Dual row-column major dram

Bandwidth boosted stacked memory

Bandwidth boosted stacked memory

Coordinated in-module RAS features for synchronous DDR compatible memory

DRAM assist error correction mechanism for DDR SDRAM interface

Asynchronous communication protocol compatible with synchronous DDR protocol

Coordinated in-module RAS features for synchronous DDR compatible memory

Asynchronous communication protocol compatible with synchronous DDR protocol

Coordinated in-module RAS features for synchronous DDR compatible memory

Page size synchronization and page size aware scheduling method for non-volatile memory dual in-line memory module (NVDIMM) over memory channel

System and method for operating a DRR-compatible asynchronous memory module

3D-stacked memory with reconfigurable compute logic

3D-stacked memory with reconfigurable compute logic

Optimized hopscotch multiple hash tables for efficient memory in-line deduplication application

Multi-cell structure for non-volatile resistive memory

Asynchronous communication protocol compatible with synchronous DDR protocol

Morphable ECC encoder/decoder for NVDIMM over DDR channel

Methods for addressing high capacity SDRAM-like memory without increasing pin cost

Refresh aware replacement policy for volatile memory cache

Hybrid memory controller with command buffer for arbitrating access to volatile and non-volatile memories in a hybrid memory group

Wear leveling for storage or memory device

Hybrid memory module and transaction-based memory interface

High performance transaction-based memory systems

ZHENG HONGZHONG

System architecture with memory channel DRAM FPGA module

NIU DIMIN

Reliability-aware memory partitioning mechanisms for future memory technologies

CHANG MU-TIEN

Dual-threshold-voltage two-port sub-threshold SRAM cell apparatus