Inventor

NIU DIMIN

US110 patents

⚠️ This page may combine multiple inventors who share the name “NIU DIMIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NIU DIMIN

SAMSUNG ELECTRONICS CO LTD

DRAM assist error correction mechanism for DDR SDRAM interface

Dataflow accelerator architecture for general matrix-matrix multiplication and tensor computation in deep learning

HBM RAS cache architecture

3-D stacked memory with reconfigurable compute logic

DRAM assist error correction mechanism for DDR SDRAM interface

ISA extension for high-bandwidth memory

Techniques to reduce read-modify-write overhead in hybrid DRAM/NAND memory

Coordinated near-far memory controller for process-in-HBM

Method to deliver in-DRAM ECC information through DDR bus

Tail response time reduction method for SSD

Hybrid memory controller for arbitrating access to volatile and non-volatile memories in a hybrid memory group

Optimized hopscotch multiple hash tables for efficient memory in-line deduplication application

Circuits and micro-architecture for a DRAM-based processing unit

DRAM assist error correction mechanism for DDR SDRAM interface

ISA extension for high-bandwidth memory

Adaptive matrix multiplication accelerator for machine learning and deep learning applications

Systems and methods for write and flush support in hybrid memory

Memory module, operation method therof, and operation method of host

DRAM assist error correction mechanism for DDR SDRAM interface

Method to deliver in-DRAM ECC information through DDR bus

Method to deliver in-DRAM ECC information through DDR bus

Coordinated in-module RAS features for synchronous DDR compatible memory

Self-optimized power management for DDR-compatible memory systems

Mitigating DRAM cache metadata access overhead with SRAM metadata cache and bloom filter

System and method for controlling a programmable deduplication ratio for a memory system

Methods for addressing high capacity SDRAM-like memory without increasing pin cost

Memory devices and modules

Virtual bucket multiple hash tables for efficient memory in-line deduplication application

DPU architecture

Software stack and programming for DPU operations

Electronic system with partitioning mechanism and method of operation thereof

High bandwidth memory system

Bandwidth boosted stacked memory

ISA extension for high-bandwidth memory

Dual row-column major dram

Bandwidth boosted stacked memory

High bandwidth memory system

Bandwidth boosted stacked memory

Coordinated in-module RAS features for synchronous DDR compatible memory

Scaling out architecture for dram-based processing unit (DPU)

DRAM assist error correction mechanism for DDR SDRAM interface

Asynchronous communication protocol compatible with synchronous DDR protocol

ALIBABA GROUP HOLDING LTD

Control of NAND flash memory for al applications

Method and device for refreshing memory

Processing accelerator architectures

ALIBABA CHINA CO LTD

Graph acceleration solution with cloud FPGA

Smart memory extension to processors

ZHENG HONGZHONG

NVDIMM adaptive access mode and smart partition mechanism

ALIBABA DAMO HANGZHOU TECH CO LTD

Processing system that increases the memory capacity of a GPGPU

NIU DIMIN

Reliability-aware memory partitioning mechanisms for future memory technologies