Inventor
BRUCE RICARDO H
US28 patents
⚠️ This page may combine multiple inventors who share the name “BRUCE RICARDO H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
BITMICRO NETWORKS INC
15 patentsUS6970890B1Nov 29, 2005
Method and apparatus for data recovery
BITMICRO NETWORKS INC102 citations98
US6529416B2Mar 4, 2003
Parallel erase operations in memory systems
BITMICRO NETWORKS INC71 citations96
US8788725B2Jul 22, 2014
Multilevel memory bus system for solid-state mass storage
BITMICRO NETWORKS INC41 citations95
US7729370B1Jun 1, 2010
Apparatus for networking devices having fibre channel node functionality
BITMICRO NETWORKS INC32 citations86
US9971524B1May 15, 2018
Scatter-gather approach for parallel data transfer in a mass storage system
BITMICRO NETWORKS INC10 citations79
US9501436B1Nov 22, 2016
Multi-level message passing descriptor
BITMICRO NETWORKS INC12 citations79
US9952991B1Apr 24, 2018
Systematic method on queuing of descriptors for multiple flash intelligent DMA engine operation
BITMICRO NETWORKS INC16 citations78
US10489318B1Nov 26, 2019
Scatter-gather approach for parallel data transfer in a mass storage system
BITMICRO NETWORKS INC6 citations68
US9875205B1Jan 23, 2018
Network of memory systems
BITMICRO NETWORKS INC2 citations68
US9798688B1Oct 24, 2017
Bus arbitration with routing and failover mechanism
BITMICRO NETWORKS INC5 citations68
US9916213B1Mar 13, 2018
Bus arbitration with routing and failover mechanism
BITMICRO NETWORKS INC2 citations67
US10459842B1Oct 29, 2019
Data storage system with configurable prefetch buffers
BITMICRO NETWORKS INC1 citations59
US10430303B1Oct 1, 2019
Bus arbitration with routing and failover mechanism
BITMICRO NETWORKS INC0 citations47
US10423554B1Sep 24, 2019
Bus arbitration with routing and failover mechanism
BITMICRO NETWORKS INC0 citations47
US10013373B1Jul 3, 2018
Multi-level message passing descriptor
BITMICRO NETWORKS INC1 citations47
BIT MICROSYSTEMS INC
4 patentsUS5956743ASep 21, 1999
Transparent management at host interface of flash-memory overhead-bytes using flash-specific DMA having programmable processor-interrupt of high-level operations
BIT MICROSYSTEMS INC258 citations98
US5822251AOct 13, 1998
Expandable flash-memory mass-storage using shared buddy lines and intermediate flash-bus between device-specific buffers and flash-intelligent DMA controllers
BIT MICROSYSTEMS INC302 citations98
US6000006ADec 7, 1999
Unified re-map and cache-index table with dual write-counters for wear-leveling of non-volatile flash RAM mass storage
BIT MICROSYSTEMS INC1,030 citations97
US6496939B2Dec 17, 2002
Method and system for controlling data in a computer system in the event of a power failure
BIT MICROSYSTEMS INC79 citations95
BITMICRO LLC
4 patentsUS10552050B1Feb 4, 2020
Multi-dimensional computer storage system
BITMICRO LLC7 citations82
US10120586B1Nov 6, 2018
Memory transaction with reduced latency
BITMICRO LLC6 citations78
US10877907B2Dec 29, 2020
Multilevel memory bus system
BITMICRO LLC3 citations70
US10133686B2Nov 20, 2018
Multilevel memory bus system
BITMICRO LLC0 citations49