Inventor · disambiguated record
Raghu Sankuratri
Also filed as: SANKURATRI RAGHU
10 granted patents·2 pending applications·250 citations·filing 1999–2015
90Inventor score
Top patents by PatentIndex Score
12 records- 0187US9123408B2Low latency synchronization scheme for mesochronous DDR systemQUALCOMM INC·Filed 2013·Granted Sep 1, 2015·10 cites·25 claims
- 0287US7804735B2Dual channel memory architecture having a reduced interface pin requirements using a double data rate scheme for the address/control signalsQUALCOMM INC·Filed 2008·Granted Sep 28, 2010·16 cites·25 claims
- 0386US9734070B2System and method for a shared cache with adaptive partitioningQUALCOMM INC·Filed 2015·Granted Aug 15, 2017·6 cites·30 claims
- 0481US6754509B1Mobile communication device having dual micro processor architecture with shared digital signal processor and shared memoryQUALCOMM INC·Filed 1999·Granted Jun 22, 2004·103 cites·20 claims
- 0580US6735454B1Method and apparatus for activating a high frequency clock following a sleep mode within a mobile station operating in a slotted paging modeQUALCOMM INC·Filed 1999·Granted May 11, 2004·96 cites·20 claims
- 0675US9612970B2Method and apparatus for flexible cache partitioning by sets and ways into component cachesQUALCOMM INC·Filed 2014·Granted Apr 4, 2017·4 cites·36 claims
- 0771US10089238B2Method and apparatus for a shared cache with dynamic partitioningQUALCOMM INC·Filed 2014·Granted Oct 2, 2018·3 cites·32 claims
- 0871US8325525B2Dual channel memory architecture having reduced interface pin requirements using a double data rate scheme for the address/control signalsMAO JIAN·Filed 2010·Granted Dec 4, 2012·4 cites·20 claims
- 0971US8098539B2Hybrid single and dual channel DDR interface scheme by interleaving address/control signals during dual channel operationSANKURATRI RAGHU·Filed 2009·Granted Jan 17, 2012·8 cites·37 claims
- 1052US9437278B2Low latency synchronization scheme for mesochronous DDR systemQUALCOMM INC·Filed 2015·Granted Sep 6, 2016·0 cites·24 claims
- 1147US2016093345A1Dynamic random access memory timing adjustmentsQUALCOMM INC·Filed 2014·Application pending·0 cites
- 1232US2005114725A1Calibrating an integrated circuit to an electronic deviceQUALCOMM INC·Filed 2003·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →