Inventor

ALEXANDER GREGORY W

US43 patents

⚠️ This page may combine multiple inventors who share the name “ALEXANDER GREGORY W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ALEXANDER GREGORY W

IBM

Method and system for handling cache coherency for self-modifying code

Zero cycle penalty in selecting instructions in prefetch buffer in the event of a miss in the instruction cache

Managing a free list of resources to decrease control complexity and reduce power consumption

Dual-issuance of microprocessor instructions using dual dependency matrices

Freelist based global completion table having both thread-specific and global completion table identifiers

Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors

Cache miss thread balancing

Slice-based allocation history buffer

Slice-based allocation history buffer

Data-less history buffer with banked restore ports in a register mapper

Error detection enhancement in a microprocessor through the use of a second dependency matrix

Cache miss thread balancing

Infinite processor thread balancing

Suppress unnecessary mapping for scratch register

Dynamic issue masks for processor hang prevention

Dynamic issue masks for processor hang prevention

Freelist based global completion table having both thread-specific and global completion table identifiers

Managing a free list of resources to decrease control complexity and reduce power consumption

Managing a free list of resources to decrease control complexity and reduce power consumption

Link stack misprediction resolution

Structure for reducing power consumption for memory device

Structure for reducing power consumption for memory device

Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions

Comparing load instruction address fields to store instruction address fields in a table to delay issuing dependent load instructions

Infinite processor thread balancing

Simplified processor sparing

Managing backend resources via frontend steering or stalls

Dynamic assignment across dispatch pipes of source ports to be used to obtain indication of physical registers

Register file mapping

ALEXANDER GREGORY W

Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors

Serializing translation lookaside buffer access around address translation parameter modification

Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions

Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors

Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions

Collecting computer processor instrumentation data

Triggering workaround capabilities based on events active in a processor pipeline

Program status word dependency handling in an out of order microprocessor design

Branch target preloading using a multiplexer and hash circuit to reduce incorrect branch predictions

DELPHI TECH INC

Apparatus and method for high efficiency operation of a high temperature fuel cell system

Hybrid power generating system combining a fuel cell and a gas turbine

Solid-oxide fuel cell system having an upstream reformate combustor

PRASKY BRIAN R

High performance cache translation look-aside buffer (TLB) lookups using multiple page size prediction

SONNELITTER III ROBERT J

Management of cache replacement status in cache memory