Inventor
BOWMAN JOSHUA W
US29 patents
Patents
29 patentsUS10949213B2Mar 16, 2021
Logical register recovery within a processor
IBM2 citations72
US10936321B2Mar 2, 2021
Instruction chaining
IBM3 citations72
US9921833B2Mar 20, 2018
Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor
IBM3 citations72
US9639418B2May 2, 2017
Parity protection of a register
IBM4 citations72
US10248426B2Apr 2, 2019
Direct register restore mechanism for distributed history buffers
IBM3 citations71
US9959123B2May 1, 2018
Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor
IBM2 citations71
US11301254B2Apr 12, 2022
Instruction streaming using state migration
IBM0 citations62
US11093282B2Aug 17, 2021
Register file write using pointers
IBM0 citations62
US11061681B2Jul 13, 2021
Instruction streaming using copy select vector
IBM0 citations62
US10719056B2Jul 21, 2020
Merging status and control data in a reservation station
IBM1 citations62
US10545765B2Jan 28, 2020
Multi-level history buffer for transaction memory in a microprocessor
IBM1 citations62
US10379867B2Aug 13, 2019
Asynchronous flush and restore of distributed history buffer
IBM1 citations62
US11360779B2Jun 14, 2022
Logical register recovery within a processor
IBM0 citations61
US11194578B2Dec 7, 2021
Fused overloaded register file read to enable 2-cycle move from condition register instruction in a microprocessor
IBM0 citations61
US11144364B2Oct 12, 2021
Supporting speculative microprocessor instruction execution
IBM1 citations60
US10956158B2Mar 23, 2021
System and handling of register data in processors
IBM0 citations60
US10909034B2Feb 2, 2021
Issue queue snooping for asynchronous flush and restore of distributed history buffer
IBM0 citations52
US10248421B2Apr 2, 2019
Operation of a multi-slice processor with reduced flush and restore latency
IBM0 citations52
US10241790B2Mar 26, 2019
Operation of a multi-slice processor with reduced flush and restore latency
IBM0 citations52
US11188332B2Nov 30, 2021
System and handling of register data in processors
IBM0 citations51
US10489253B2Nov 26, 2019
On-demand GPR ECC error detection and scrubbing for a multi-slice microprocessor
IBM0 citations51
US9928073B2Mar 27, 2018
Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor
IBM0 citations51
US9858078B2Jan 2, 2018
Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor
IBM0 citations50
US11068267B2Jul 20, 2021
High bandwidth logical register flush recovery
IBM0 citations49
US11403109B2Aug 2, 2022
Steering a history buffer entry to a specific recovery port during speculative flush recovery lookup in a processor
IBM0 citations48
US10740140B2Aug 11, 2020
Flush-recovery bandwidth in a processor
IBM0 citations48
US10740107B2Aug 11, 2020
Operation of a multi-slice processor implementing load-hit-store handling
IBM0 citations41
US10445100B2Oct 15, 2019
Broadcasting messages between execution slices for issued instructions indicating when execution results are ready
IBM0 citations41
US10318294B2Jun 11, 2019
Operation of a multi-slice processor implementing dependency accumulation instruction sequencing
IBM0 citations37