Inventor

DESHPANDE NITIN A

US54 patents

⚠️ This page may combine multiple inventors who share the name “DESHPANDE NITIN A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DESHPANDE NITIN A

INTEL CORP

Integrated circuit package with embedded bridge

Embedded multi-device bridge with through-bridge conductive via signal connection

Low cost package warpage solution

Microelectronic structures including bridges

Microelectronic structures including bridges

Low cost package warpage solution

Integrated circuit package with embedded bridge

Integrated circuit package with embedded bridge

Picture frame stiffeners for microelectronic packages

Underfill material flow control for reduced die-to-die spacing in semiconductor packages

Microelectronic structures including bridges

Photonic integrated circuit packaging architectures

Photonic integrated circuit packaging architectures

Low cost package warpage solution

Embedded multi-device bridge with through-bridge conductive via signal connection

Embedded multi-device bridge with through-bridge conductive via signal connection

Electro-magnetic interference (EMI) shielding techniques and configurations

Active bridge enabled co-packaged photonic transceiver

Warpage control for microelectronics packages

Die warpage control for thin die assembly

Nested glass packaging architecture for hybrid electrical and optical communication devices

Covered cavity for a photonic integrated circuit (PIC)

HBI die fiducial architecture with cantilever fiducials for smaller die size and better yields

HBI die architecture with fiducial in street for no metal depopulation in active die

Microelectronic package with substrate cavity for bridge-attach

Low cost package warpage solution

Microelectronic structures including bridges

Microelectronic structures including bridges

Low cost package warpage solution

Microelectronic structures including bridges

Antenna boards and communication devices

Mold material architecture for package device structures

Method and materials for warpage thermal and interconnect solutions

Electro-magnetic interference (EMI) shielding techniques and configurations

High density interconnection of microelectronic devices

Method for reducing assembly-induced stress in a semiconductor die

Package architecture of photonic system with vertically stacked dies having planarized edges

Photonic integrated circuit packaging architecture

Warpage control for microelectronics packages

Method, system, and apparatus for gravity assisted chip attachment

Multichip semiconductor package including a bridge die disposed in a cavity having non-planar interconnects

Microelectronic structures including bridges

Microelectronic structure including active base substrate with through vias between a top die and a bottom die supported on an interposer

Microelectronic structures including bridges

Low cost package warpage solution

High density interconnection of microelectronic devices

Picture frame stiffeners for microelectronic packages

Package architecture of scalable compute wall having compute bricks with vertically stacked dies

KARHADE OMKAR G

Methods to form high density through-mold interconnections

TAHOE RES LTD

Underfill material flow control for reduced die-to-die spacing in semiconductor packages