P

Inventor

NICKERSON ROBERT M

US27 patents
⚠️ This page may combine multiple inventors who share the name “NICKERSON ROBERT M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

24 patents
US8987918B2Mar 24, 2015

Interconnect structures with polymer core

INTEL CORP54 citations98
US7304373B2Dec 4, 2007

Power distribution within a folded flex package method and apparatus

INTEL CORP83 citations96
US7358444B2Apr 15, 2008

Folded substrate with interposer package for integrated circuit devices

INTEL CORP34 citations89
US10607976B2Mar 31, 2020

Offset interposers for large-bottom packages and large-die package-on-package structures

INTEL CORP6 citations83
US10121722B1Nov 6, 2018

Architecture material and process to improve thermal performance of the embedded die package

INTEL CORP12 citations82
US6794760B1Sep 21, 2004

Integrated circuit interconnect

INTEL CORP15 citations76
US9691728B2Jun 27, 2017

BBUL top side substrate layer enabling dual sided silicon interconnect and stacking flexibility

INTEL CORP3 citations73
US12107082B2Oct 1, 2024

Offset interposers for large-bottom packages and large-die package-on-package structures

INTEL CORP2 citations72
US11978730B2May 7, 2024

Offset interposers for large-bottom packages and large-die package-on-package structures

INTEL CORP1 citations72
US11798932B2Oct 24, 2023

Offset interposers for large-bottom packages and large-die package-on-package structures

INTEL CORP1 citations72
US11056466B2Jul 6, 2021

Package on package thermal transfer systems and methods

INTEL CORP0 citations62
US12417958B2Sep 16, 2025

Microelectronics package comprising a package-on-package (PoP) architecture with inkjet barrier material for controlling bondline thickness and PoP adhesive keep out zone

INTEL CORP0 citations59
US12347743B2Jul 1, 2025

Microelectronics package comprising a package-on-package (PoP) architecture with inkjet barrier material for controlling bondline thickness and pop adhesive keep out zone

INTEL CORP0 citations59
US12315777B2May 27, 2025

Microelectronics package comprising a package-on-package (POP) architecture with inkjet barrier material for controlling bondline thickness and POP adhesive keep out zone

INTEL CORP0 citations59
US12406906B2Sep 2, 2025

Through mold interconnect drill feature

INTEL CORP0 citations58
US11705383B2Jul 18, 2023

Through mold interconnect drill feature

INTEL CORP0 citations58
US12394773B2Aug 19, 2025

Laser ablation-based surface property modification and contamination removal

INTEL CORP0 citations55
US12362340B2Jul 15, 2025

Laser ablation-based surface property modification and contamination removal

INTEL CORP0 citations55
US10438930B2Oct 8, 2019

Package on package thermal transfer systems and methods

INTEL CORP0 citations52
US10128225B2Nov 13, 2018

Interconnect structures with polymer core

INTEL CORP0 citations52
US9613934B2Apr 4, 2017

Interconnect structures with polymer core

INTEL CORP0 citations52
US9691727B2Jun 27, 2017

Pad-less interconnect for electrical coreless substrate

INTEL CORP0 citations51
US7818878B2Oct 26, 2010

Integrated circuit device mounting with folded substrate and interposer

INTEL CORP0 citations48
US11222877B2Jan 11, 2022

Thermally coupled package-on-package semiconductor packages

INTEL CORP0 citations47

GANESAN SANKA

1 patent

MORTENSEN RUSSELL K

1 patent

ARANA LEONEL R

1 patent