P

Inventor

SAHU RAHUL

IN32 patents
⚠️ This page may combine multiple inventors who share the name “SAHU RAHUL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

QUALCOMM INC

21 patents
US9865337B1Jan 9, 2018

Write data path to reduce charge leakage of negative boost

QUALCOMM INC20 citations94
US9455028B1Sep 27, 2016

Adaptive negative bit line write assist

QUALCOMM INC29 citations94
US9916892B1Mar 13, 2018

Write driver circuitry to reduce leakage of negative boost charge

QUALCOMM INC10 citations84
US11049552B1Jun 29, 2021

Write assist circuitry for memory

QUALCOMM INC7 citations83
US11955169B2Apr 9, 2024

High-speed multi-port memory supporting collision

QUALCOMM INC4 citations74
US9928898B2Mar 27, 2018

Wordline adjustment scheme

QUALCOMM INC5 citations73
US10811088B2Oct 20, 2020

Access assist with wordline adjustment with tracking cell

QUALCOMM INC5 citations72
US10614865B1Apr 7, 2020

Boost generation circuitry for memory

QUALCOMM INC3 citations72
US11152921B1Oct 19, 2021

Systems and methods for control signal latching in memories

QUALCOMM INC2 citations71
US9721650B1Aug 1, 2017

Architecture to improve write-ability in SRAM

QUALCOMM INC6 citations71
US10811086B1Oct 20, 2020

SRAM write yield enhancement with pull-up strength modulation

QUALCOMM INC2 citations68
US12327599B2Jun 10, 2025

Memory with scan chain testing of column redundancy logic and multiplexing

QUALCOMM INC0 citations62
US12183393B2Dec 31, 2024

High-speed multi-port memory supporting collision

QUALCOMM INC0 citations62
US11935606B2Mar 19, 2024

Memory with scan chain testing of column redundancy logic and multiplexing

QUALCOMM INC1 citations62
US11837313B2Dec 5, 2023

Memory with efficient DVS controlled by asynchronous inputs

QUALCOMM INC0 citations62
US10867668B2Dec 15, 2020

Area efficient write data path circuit for SRAM yield enhancement

QUALCOMM INC1 citations62
US11972834B2Apr 30, 2024

Low power and robust level-shifting pulse latch for dual-power memories

QUALCOMM INC0 citations61
US12020766B2Jun 25, 2024

Memory circuit architecture with multiplexing between memory banks

QUALCOMM INC1 citations58
US12047073B2Jul 23, 2024

Power supply circuit with reduced leakage current

QUALCOMM INC0 citations51
US12020746B2Jun 25, 2024

Memory write assist with reduced switching power

QUALCOMM INC0 citations44
US10839866B1Nov 17, 2020

Memory core power-up with reduced peak current

QUALCOMM INC0 citations38

LSI CORP

8 patents

SAHU RAHUL

1 patent

LSI COPORATION

1 patent

Vikash

1 patent