Inventor
GUPTA SHARAD KUMAR
IN26 patents
⚠️ This page may combine multiple inventors who share the name “GUPTA SHARAD KUMAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
QUALCOMM INC
25 patentsUS10446196B1Oct 15, 2019
Flexible power sequencing for dual-power memory
QUALCOMM INC16 citations84
US9928889B1Mar 27, 2018
Bitline precharge control and tracking scheme providing increased memory cycle speed for pseudo-dual-port memories
QUALCOMM INC17 citations84
US9837144B1Dec 5, 2017
Apparatus and method for controlling boost capacitance for low power memory circuits
QUALCOMM INC12 citations84
US11049552B1Jun 29, 2021
Write assist circuitry for memory
QUALCOMM INC7 citations83
US9947419B1Apr 17, 2018
Apparatus and method for implementing design for testability (DFT) for bitline drivers of memory circuits
QUALCOMM INC13 citations83
US9875790B1Jan 23, 2018
Boost charge recycle for low-power memory
QUALCOMM INC14 citations82
US11955169B2Apr 9, 2024
High-speed multi-port memory supporting collision
QUALCOMM INC4 citations74
US9928898B2Mar 27, 2018
Wordline adjustment scheme
QUALCOMM INC5 citations73
US10811088B2Oct 20, 2020
Access assist with wordline adjustment with tracking cell
QUALCOMM INC5 citations72
US11152921B1Oct 19, 2021
Systems and methods for control signal latching in memories
QUALCOMM INC2 citations71
US9721650B1Aug 1, 2017
Architecture to improve write-ability in SRAM
QUALCOMM INC6 citations71
US9607674B1Mar 28, 2017
Pulse latch reset tracking at high differential voltage
QUALCOMM INC4 citations71
US10811086B1Oct 20, 2020
SRAM write yield enhancement with pull-up strength modulation
QUALCOMM INC2 citations68
US12327599B2Jun 10, 2025
Memory with scan chain testing of column redundancy logic and multiplexing
QUALCOMM INC0 citations62
US12183393B2Dec 31, 2024
High-speed multi-port memory supporting collision
QUALCOMM INC0 citations62
US11935606B2Mar 19, 2024
Memory with scan chain testing of column redundancy logic and multiplexing
QUALCOMM INC1 citations62
US11837313B2Dec 5, 2023
Memory with efficient DVS controlled by asynchronous inputs
QUALCOMM INC0 citations62
US10867668B2Dec 15, 2020
Area efficient write data path circuit for SRAM yield enhancement
QUALCOMM INC1 citations62
US11972834B2Apr 30, 2024
Low power and robust level-shifting pulse latch for dual-power memories
QUALCOMM INC0 citations61
US12020766B2Jun 25, 2024
Memory circuit architecture with multiplexing between memory banks
QUALCOMM INC1 citations58
US12047073B2Jul 23, 2024
Power supply circuit with reduced leakage current
QUALCOMM INC0 citations51
US9875776B1Jan 23, 2018
Bit writability implementation for memories
QUALCOMM INC1 citations51
US9865316B2Jan 9, 2018
Memory with a word line assertion delayed by a bit line discharge for write operations with improved write time and reduced write power
QUALCOMM INC1 citations50
US10140224B2Nov 27, 2018
Noise immune data path scheme for multi-bank memory architecture
QUALCOMM INC0 citations45
US11228312B1Jan 18, 2022
Wide voltage range level shifter with reduced duty cycle distortion across operating conditions
QUALCOMM INC0 citations40