Inventor

LANGE RONALD E

23 patents

⚠️ This page may combine multiple inventors who share the name “LANGE RONALD E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LANGE RONALD E

BULL HN INFORMATION SYST

Automated safestore stack generation and recovery in a fault tolerant central processor

Sharing of register stack by two execution units in a central processor

Binary to binary coded decimal and binary coded decimal to binary conversion in a VLSI central processing unit

Safestore frame implementation in a central processor

Efficient error detection in a vlsi central processing unit

Central processor with duplicate basic processing units employing multiplexed data signals to reduce inter-unit conductor count

Central processor with duplicate basic processing units employing multiplexed cache store control signals to reduce inter-unit conductor count

Central processing unit incorporation selectable, precisa ratio, speed of execution derating

Basic operations synchronization and local mode controller in a VLSI central processor

Method and apparatus for minimizing the number of control words in a brom control store of a microprogrammed central processor

Method for reducing control store space in a VLSI central processor

HONEYWELL INF SYSTEMS

Cache memory utilizing selective clearing and least recently used updating

Microprocessor based maintenance system

Apparatus for recording the order of usage of locations in memory

Maintenance panel for communicating with an automated maintenance system

Interface circuit for coupling an automated maintenance system to a CPU

Low cost programmable video computer terminal

Microprocessor based computer terminal

KONINKL PHILIPS ELECTRONICS NV

PCI bridge having latency inducing serial bus

PCI bridge configuration having physically separate parts

HONEYWELL BULL

Apparatus for forcing a reload from main memory upon cache memory error

BULL HN INFORMATIONS SYSTEMS I

Automated safestore stack generation and move in a fault tolerant central processor

BULL INFORMATION SYSTEMS INC

Error detection in the basic processing unit of a VLSI central processor