Inventor

SEMMELMEYER MARK

US12 patents

⚠️ This page may combine multiple inventors who share the name “SEMMELMEYER MARK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MICROUNITY SYSTEMS ENG

3 patents

US5867735AFeb 2, 1999

Method for storing prioritized memory or I/O transactions in queues having one priority level less without changing the priority when space available in the corresponding queues exceed

MICROUNITY SYSTEMS ENG61 citations96

US5812799ASep 22, 1998

Non-blocking load buffer and a multiple-priority memory system for real-time multiprocessing

MICROUNITY SYSTEMS ENG68 citations96

US5737547AApr 7, 1998

System for placing entries of an outstanding processor request into a free pool after the request is accepted by a corresponding peripheral device

MICROUNITY SYSTEMS ENG40 citations92

ORACLE INT CORP

3 patents

US11561923B2Jan 24, 2023

CHIPS & TECH INC

2 patents

US5325516AJun 28, 1994

Processor system with dual clock

CHIPS & TECH INC22 citations91

US5381543AJan 10, 1995

Processor system with dual clock

CHIPS & TECH INC16 citations80

AMDAHL CORP

1 patent

US5095424AMar 10, 1992

Computer system architecture implementing split instruction and operand cache line-pair-state management

AMDAHL CORP64 citations94

SEMMELMEYER MARK

1 patent

US8686570B2Apr 1, 2014

Multi-dimensional integrated circuit structures and methods of forming the same

SEMMELMEYER MARK38 citations91

TAIWAN SEMICONDUCTOR MFG

1 patent

US9054101B2Jun 9, 2015

Multi-dimensional integrated circuit structures and methods of forming the same

TAIWAN SEMICONDUCTOR MFG13 citations84

TAIWAN SEMICONDUCTOR MFG CO LTD

1 patent

US9686852B2Jun 20, 2017

Multi-dimensional integrated circuit structures and methods of forming the same

TAIWAN SEMICONDUCTOR MFG CO LTD3 citations73

SEMMELMEYER MARK

MICROUNITY SYSTEMS ENG

Method for storing prioritized memory or I/O transactions in queues having one priority level less without changing the priority when space available in the corresponding queues exceed

Non-blocking load buffer and a multiple-priority memory system for real-time multiprocessing

System for placing entries of an outstanding processor request into a free pool after the request is accepted by a corresponding peripheral device

ORACLE INT CORP

Method for training multichannel data receiver timing

Method for training multichannel data receiver timing

Narrow-parallel scan-based device testing

CHIPS & TECH INC

Processor system with dual clock

Processor system with dual clock

AMDAHL CORP

Computer system architecture implementing split instruction and operand cache line-pair-state management

SEMMELMEYER MARK

Multi-dimensional integrated circuit structures and methods of forming the same

TAIWAN SEMICONDUCTOR MFG

Multi-dimensional integrated circuit structures and methods of forming the same

TAIWAN SEMICONDUCTOR MFG CO LTD

Multi-dimensional integrated circuit structures and methods of forming the same