Inventor
RONCHETTI BRUCE JOSEPH
US26 patents
⚠️ This page may combine multiple inventors who share the name “RONCHETTI BRUCE JOSEPH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
24 patentsUS6349382B1Feb 19, 2002
System for store forwarding assigning load and store instructions to groups and reorder queues to keep track of program order
IBM56 citations96
US6266768B1Jul 24, 2001
System and method for permitting out-of-order execution of load instructions
IBM63 citations96
US6237081B1May 22, 2001
Queuing method and apparatus for facilitating the rejection of sequential instructions in a processor
IBM81 citations96
US9690586B2Jun 27, 2017
Processing of multiple instruction streams in a parallel slice processor
IBM26 citations94
US9690585B2Jun 27, 2017
Parallel slice processor with dynamic instruction stream mapping
IBM22 citations94
US9672043B2Jun 6, 2017
Processing of multiple instruction streams in a parallel slice processor
IBM29 citations94
US9665372B2May 30, 2017
Parallel slice processor with dynamic instruction stream mapping
IBM25 citations94
US7350051B2Mar 25, 2008
Method to optimize effective page number to real page number translation path from page table entries match resumption of execution stream
IBM15 citations92
US6640293B1Oct 28, 2003
Apparatus and method of utilizing Alias Hit signals to detect errors within the real address tag arrays
IBM21 citations92
US6484230B1Nov 19, 2002
Method and system for speculatively processing a load instruction before completion of a preceding synchronization instruction
IBM32 citations92
US6336168B1Jan 1, 2002
System and method for merging multiple outstanding load miss instructions
IBM46 citations92
US6301654B1Oct 9, 2001
System and method for permitting out-of-order execution of load and store instructions
IBM34 citations89
US9977678B2May 22, 2018
Reconfigurable parallel execution and load-store slice processor
IBM7 citations84
US9971602B2May 15, 2018
Reconfigurable processing method with modes controlling the partitioning of clusters and cache slices
IBM6 citations84
US7318127B2Jan 8, 2008
Method, apparatus, and computer program product for sharing data in a cache among threads in an SMT processor
IBM17 citations84
US7284094B2Oct 16, 2007
Mechanism and apparatus allowing an N-way set associative cache, implementing a hybrid pseudo-LRU replacement algorithm, to have N L1 miss fetch requests simultaneously inflight regardless of their congruence class
IBM14 citations84
US10983800B2Apr 20, 2021
Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slices
IBM2 citations73
US10157064B2Dec 18, 2018
Processing of multiple instruction streams in a parallel slice processor
IBM2 citations73
US10083039B2Sep 25, 2018
Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slices
IBM3 citations73
US7380062B2May 27, 2008
Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatch
IBM5 citations73
US6178497B1Jan 23, 2001
System and method for determining the relative age of instructions in a processor
IBM14 citations71
US6490653B1Dec 3, 2002
Method and system for optimally issuing dependent instructions based on speculative L2 cache hit in a data processing system
IBM4 citations62
US7752354B2Jul 6, 2010
Auxiliary mechanism to manage instruction restart and restart coming in a lookahead processor
IBM1 citations51
US7660965B2Feb 9, 2010
Method to optimize effective page number to real page number translation path from page table entries match resumption of execution stream
IBM1 citations51