Inventor

PARDO ILAN

IL61 patents

⚠️ This page may combine multiple inventors who share the name “PARDO ILAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PARDO ILAN

INTEL CORP

PCI express enhancements and extensions

Apparatus and method for low-latency invocation of accelerators

Method, system, and apparatus for rerouting interrupts in a multi-core processor

PCI express enhancements and extensions

PCI express enhancements and extensions

Apparatus and method for low-latency invocation of accelerators

Atomic operations in PCI express

PCI express transaction descriptor

Transaction re-ordering

Prefectching in PCI express

Apparatus and method for a hybrid latency-throughput processor

User-level fork and join processors, methods, systems, and instructions

Method and apparatus to reduce idle link power in a platform

Apparatus to reduce idle link power in a platform

Apparatus and method for a hybrid latency-throughput processor

Memory address collision detection of ordered parallel threads with bloom filters

Instructions and logic to provide atomic range modification operations

Transaction layer packet formatting

Method and apparatus to reduce idle link power in a platform

Apparatus and method for invocation of a multi threaded accelerator

Apparatus and method for retrieving elements from a linked structure

Apparatus and method for low-latency invocation of accelerators

AJANOVIC JASMIN

PCI express enhancements and extensions

PCI express enhancements and extensions

PCI express enhancements and extensions

PCI express enhancements and extensions including device window caching

PCI express enhancements and extensions

PCI express enhancements and extensions

PCI express enhancements and extensions including transactions having prefetch parameters

PCI express enhancements and extensions

Atomic operations

MELLANOX TECHNOLOGIES LTD

Implementing hierarchical PCI express switch topology over coherent mesh interconnect

Prefetching of completion notifications and context

Payload cache

Maintaining data confidentiality in shared computing environments

Programmable core integrated with hardware pipeline of network interface device

Processor with conditional-fence commands excluding designated memory regions

Processor supporting vectored system calls

Processor with instructions for resetting multiple registers

Expandable queue

MOTOROLA INC

Apparatus and method for implementing watchpoints and breakpoints in a data processing system

Data processing system and method for testing a data processor having a cache memory

Method and apparatus for communicating between master and slave electronic devices where the slave device may be hazardous

PARDO ILAN

Compression format for high bandwidth dictionary compression

Snoop filter having centralized translation circuitry and shadow tag array

Method and apparatus for high bandwidth dictionary compression technique using set update dictionary update policy

APPLIED MICRO CIRCUITS CORP

Dynamic allocation of packets to tasks

Asymmetric coherency protection

BEN-KIKI OREN

Apparatus and method for fast failure handling of instructions

DIEFENBAUGH PAUL S

Method and apparatus to reduce idle link power in a platform