Inventor

SADANA DEVENDRA K

US752 patents

⚠️ This page may combine multiple inventors who share the name “SADANA DEVENDRA K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SADANA DEVENDRA K

IBM

SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device

Silicon-on-insulator vertical array device trench capacitor DRAM

Ultimate SIMOX

Process of making densely patterned silicon-on-insulator (SOI) region on a wafer

Semiconductor chip having tampering feature

Monolithic visible-infrared focal plane array on silicon

Relaxed, low-defect SGOI for strained Si CMOS applications

Strained silicon CMOS on hybrid crystal orientations

Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer

Fin FET devices from bulk semiconductor and method for forming

Silicon-on-insulator vertical array DRAM cell with self-aligned buried strap

Method of preventing surface roughening during hydrogen prebake of SiGe substrates

Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal

Method of creating high-quality relaxed SiGe-on-insulator for strained Si CMOS applications

Process of fabricating planar and densely patterned silicon-on-insulator structure

3D integrated DC-DC power converters

Monolithic integrated photonics with lateral bipolar and BiCMOS

Wafer scale epitaxial graphene transfer

Reduction of defect induced leakage in III-V semiconductor devices

Optoelectronics and CMOS integration on GOI substrate

Integrating active matrix inorganic light emitting diodes for display devices

III-V finFETs on silicon substrate

Thin light emitting diode and fabrication method

Ultra-thin Si MOSFET device structure and method of manufacture

Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer

Method to form Si-containing SOI and underlying substrate with different orientations

Method for fabricating SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) substrates

Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal

Relaxed, low-defect SGOI for strained Si CMOS applications

BICMOS technology on SIMOX wafers

Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal

Patterned SOI by oxygen implantation and annealing

Use of hydrogen implantation to improve material properties of silicon-germanium-on-insulator material made by thermal diffusion

Method of improving the quality of defective semiconductor material

Self-adjusting thickness uniformity in SOI by high-temperature oxidation of SIMOX and bonded SOI

Densely patterned silicon-on-insulator (SOI) region on a wafer

Nano-pillar-based biosensing device

Light emitting diodes with via contact scheme

Thin film wafer transfer and structure for electronic devices

CMOS transistors with stressed high mobility channels

Field effect transistor with stressed channel and method for making same

Patterned strained silicon for high performance circuits

Formation of patterned silicon-on-insulator (SOI)/silicon-on-nothing (SON) composite structure by porous Si engineering

Method of forming a SiGe-on-insulator substrate using separation by implantation of oxygen

Control of buried oxide quality in low dose SIMOX

BEDELL STEPHEN W

Integrating active matrix inorganic light emitting diodes for display devices

Strained CMOS device, circuit and method of fabrication

Breakdown voltage multiplying integration scheme

KIM JEE HWAN

N-type carrier enhancement in semiconductors

GLOBALFOUNDRIES INC

Implant-free punch through doping layer formation for bulk FinFET structures