Inventor

RAWAT HARSH

IN27 patents

⚠️ This page may combine multiple inventors who share the name “RAWAT HARSH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RAWAT HARSH

ST MICROELECTRONICS INT NV

Pseudo dual port memory using a dual port cell and a single port cell with associated valid data bits and related methods

Adaptive bit line overdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

Serial word line actuation with linked source voltage supply modulation for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

Static random access memory supporting a single clock cycle read-modify-write operation

Configurable pseudo dual port architecture for use with single port SRAM

Configurable pseudo dual port architecture for use with single port SRAM

Low voltage selftime tracking circuitry for write assist based memory operation

In-memory computation circuit using static random access memory (SRAM) array segmentation

Bit-cell architecture based in-memory compute

SRAM with fast, controlled peak current, power efficient array reset, and data corruption modes for secure applications

Enhanced accuracy of bit line reading for an in-memory compute operation by accounting for variation in read current

Bit line read current mirroring circuit for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

Memory architecture supporting both conventional memory access mode and digital in-memory computation processing mode

Adaptive word line underdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

Selective bit line clamping control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

Adaptive body bias management for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

Built-in self test circuit for segmented static random access memory (SRAM) array input/output

At-speed transition fault testing for a multi-port and multi-clock memory

Tuning of read/write cycle time delay for a memory circuit dependent on operational mode selection

Static random access memory supporting a single clock cycle read-modify-write operation with a modulated word line assertion

Built-in self test circuit for segmented static random access memory (SRAM) array input/output

Low power and fast memory reset

Modular memory architecture with gated sub-array operation dependent on stored data content

Repair control logic for safe memories having redundant elements

Cache memory system with simultaneous read-write in single cycle

MISHRA ANAND KUMAR

Balanced sense amplifier for single ended bitline memory architecture

ROY TANMOY

Method and apparatus for testing of a memory with redundancy elements