Inventor

DHORI KEDAR JANARDAN

IN26 patents

⚠️ This page may combine multiple inventors who share the name “DHORI KEDAR JANARDAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DHORI KEDAR JANARDAN

ST MICROELECTRONICS INT NV

Temperature compensated read assist circuit for a static random access memory (SRAM)

Adaptive bit line overdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

Method and apparatus for enhancing read stability of a static random access memory circuit in low voltage operation

Circuit for generating a sense amplifier enable signal with variable timing

Serial word line actuation with linked source voltage supply modulation for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

In-memory computation circuit using static random access memory (SRAM) array segmentation

Bit-cell architecture based in-memory compute

Circuitry for adjusting retention voltage of a static random access memory (SRAM)

Method and apparatus for enhancing read stability of a static random access memory circuit in low voltage operation

Enhanced accuracy of bit line reading for an in-memory compute operation by accounting for variation in read current

Bit line read current mirroring circuit for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

Device and method for reading data from memory cells

Memory architecture supporting both conventional memory access mode and digital in-memory computation processing mode

Adaptive word line underdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

Selective bit line clamping control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

Adaptive body bias management for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

Built-in self test circuit for segmented static random access memory (SRAM) array input/output

At-speed transition fault testing for a multi-port and multi-clock memory

Tuning of read/write cycle time delay for a memory circuit dependent on operational mode selection

Built-in self test circuit for segmented static random access memory (SRAM) array input/output

Repair control logic for safe memories having redundant elements

SRAM cell layout including arrangement of multiple active regions and multiple gate regions

ST MICROELECTRONICS SRL

Computing system power management device, system and method

Computing system power management device, system and method

STMICROELECTRONICS FRANCE

Silicon-on-insulator semiconductor device with a static random access memory circuit

DHORI KEDAR JANARDAN

Single-ended bit line based storage system