Inventor

AYODHYAWASI MANUJ

IN19 patents

⚠️ This page may combine multiple inventors who share the name “AYODHYAWASI MANUJ”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

AYODHYAWASI MANUJ

ST MICROELECTRONICS INT NV

Adaptive bit line overdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

Serial word line actuation with linked source voltage supply modulation for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

In-memory computation circuit using static random access memory (SRAM) array segmentation

Bit-cell architecture based in-memory compute

Enhanced accuracy of bit line reading for an in-memory compute operation by accounting for variation in read current

Bit line read current mirroring circuit for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

Memory architecture supporting both conventional memory access mode and digital in-memory computation processing mode

Adaptive word line underdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

Selective bit line clamping control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

Adaptive body bias management for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

Built-in self test circuit for segmented static random access memory (SRAM) array input/output

At-speed transition fault testing for a multi-port and multi-clock memory

Tuning of read/write cycle time delay for a memory circuit dependent on operational mode selection

Built-in self test circuit for segmented static random access memory (SRAM) array input/output

ST MICROELECTRONICS SRL

Tagged memory operated at lower VMIN in error tolerant system

Variable clock adaptation in neural network processors

Tagged memory operated at lower vmin in error tolerant system

Tagged memory operated at lower vmin in error tolerant system

AYODHYAWASI MANUJ

Interconnect structure and method in programmable devices