Inventor
MORAN SEAN
GB42 patents
⚠️ This page may combine multiple inventors who share the name “MORAN SEAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
JPMORGAN CHASE BANK NA
25 patentsUS11868768B2Jan 9, 2024
Detecting secrets in source code
JPMORGAN CHASE BANK NA2 citations67
US11853278B2Dec 26, 2023
Systems and methods for combining graph embedding and random forest classification for improving classification of distributed ledger activities
JPMORGAN CHASE BANK NA0 citations60
US12481634B2Nov 25, 2025
Systems and methods for counteracting data-skewness for locality sensitive hashing via feature selection and pruning
JPMORGAN CHASE BANK NA0 citations59
US12229100B2Feb 18, 2025
Systems and methods for counteracting data-skewness for locality sensitive hashing via feature selection and pruning
JPMORGAN CHASE BANK NA0 citations59
US12242829B2Mar 4, 2025
Systems and methods for source code understanding using spatial representations
JPMORGAN CHASE BANK NA0 citations53
US12050573B2Jul 30, 2024
Systems and methods for streaming classification of distributed ledger-based activities
JPMORGAN CHASE BANK NA0 citations53
US11775265B2Oct 3, 2023
Method and system for library package management
JPMORGAN CHASE BANK NA1 citations53
US12361363B2Jul 15, 2025
Method and system for proficiency identification
JPMORGAN CHASE BANK NA0 citations49
US12554618B2Feb 17, 2026
Systems and methods for prediction of test failures
JPMORGAN CHASE BANK NA0 citations48
US12284160B2Apr 22, 2025
Systems and methods for federated secure vocabulary learning
JPMORGAN CHASE BANK NA0 citations48
US12379923B2Aug 5, 2025
Systems and method for automated code analysis and tagging
JPMORGAN CHASE BANK NA0 citations47
US12008365B2Jun 11, 2024
Systems and method for automated code analysis and tagging
JPMORGAN CHASE BANK NA0 citations47
US11921896B2Mar 5, 2024
Systems and methods for anonymizing a dataset of biometric data while retaining data utility
JPMORGAN CHASE BANK NA0 citations47
US12400430B2Aug 26, 2025
Systems and methods for noise agnostic federated learning
JPMORGAN CHASE BANK NA0 citations45
US12393401B2Aug 19, 2025
Systems and methods for improving efficiency and control compliance across software development life cycles using domain-specific controls
JPMORGAN CHASE BANK NA0 citations45
US12386979B2Aug 12, 2025
Systems and methods for federated model validation and data verification
JPMORGAN CHASE BANK NA0 citations45
US12159127B2Dec 3, 2024
Systems and methods for detecting code duplication in codebases
JPMORGAN CHASE BANK NA0 citations45
US12039296B2Jul 16, 2024
Systems and methods for auto-captioning repositories from source code
JPMORGAN CHASE BANK NA0 citations45
US11625423B2Apr 11, 2023
Linear late-fusion semantic structural retrieval
JPMORGAN CHASE BANK NA0 citations45
US12197911B2Jan 14, 2025
Systems and methods for multi-signal pattern matching with graph propagation
JPMORGAN CHASE BANK NA0 citations44
US12182547B2Dec 31, 2024
Systems and methods for code repository embedding for tagging and summarization tasks using attention on multiple code domains
JPMORGAN CHASE BANK NA0 citations44
US11782700B2Oct 10, 2023
Method and system for automatic assignment of code topics
JPMORGAN CHASE BANK NA0 citations43
US12524723B2Jan 13, 2026
Systems and methods for risk diagnosis of cryptocurrency addresses on blockchains using anonymous and public information
JPMORGAN CHASE BANK NA0 citations42
US12580818B2Mar 17, 2026
Systems and methods for anomaly detection in software-defined networks from observed host metrics
JPMORGAN CHASE BANK NA0 citations37
US12536236B2Jan 27, 2026
Systems and methods for generating document formatting and content using generative AI
JPMORGAN CHASE BANK NA0 citations34
INVENSAS CORP
3 patentsUS9490195B1Nov 8, 2016
Wafer-level flipped die stacks with leadframes or metal foil interconnects
INVENSAS CORP27 citations94
US9917042B2Mar 13, 2018
2.5D microelectronic assembly and method with circuit structure formed on carrier
INVENSAS CORP3 citations73
US9666513B2May 30, 2017
Wafer-level flipped die stacks with leadframes or metal foil interconnects
INVENSAS CORP0 citations52