Inventor

PAN KUO-HUA

TW104 patents

⚠️ This page may combine multiple inventors who share the name “PAN KUO-HUA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PAN KUO-HUA

TAIWAN SEMICONDUCTOR MFG CO LTD

FinFET structure with controlled air gaps

Sidewall spacers for self-aligned contacts

Semiconductor devices having gate dielectric layers of varying thicknesses and methods of forming the same

Gate-all-around (GAA) method and devices

Semiconductor device and manufacturing method thereof

Vias for cobalt-based interconnects and methods of fabrication thereof

Contact plugs and methods forming same

Reducing parasitic capacitance in field-effect transistors

Semiconductor structure with extended contact structure

Epitaxial blocking layer for multi-gate devices and fabrication methods thereof

Vias for cobalt-based interconnects and methods of fabrication thereof

Semiconductor devices having gate dielectric layers of varying thicknesses and methods of forming the same

Semiconductor device and manufacturing method thereof

Hybrid nanostructure and fin structure device

Semiconductor structures including standard cells and tap cells

Semiconductor device structure and method for forming the same

Epitaxial blocking layer for multi-gate devices and fabrication methods thereof

Semiconductor device and method of forming the same

Method for manufacturing semiconductor structure with extended contact structure

Gate-all-around structure with dummy pattern top in channel region and methods of forming the same

Semiconductor device and manufacturing method thereof

Nanosheet CMOS device and method of forming

Method of forming a gate structure of a semiconductor device

Semiconductor device gate structure and method of fabricating thereof

Semiconductor device structure with uniform threshold voltage distribution and method of forming the same

Gate structure and method

Contact plugs and methods forming same

Hybrid nanostructure and fin structure device

Reducing parasitic capacitance in field-effect transistors

Semiconductor strutures with dielectric fins

Semiconductor structure and methods of forming the same

Semiconductor devices and methods of manufacture

Structure and method for FinFET device with source/drain modulation

Isolation structures

Semiconductor devices having gate dielectric layers of varying thicknesses and methods of forming the same

Gate spacers and methods of forming the same in semiconductor devices

Semiconductor devices and methods of manufacture

Semiconductor structure and methods of forming the same

Gate structure and method

Structure and method for FinFET device with source/drain modulation

Reducing parasitic capacitance in field-effect transistors

Gate structure and method

Semiconductor device and method of forming the same

FinFET structure with controlled air gaps

TAIWAN SEMICONDUCTOR MFG

Method of forming an aluminum protection guard structure for a copper metal structure

Ultra-shallow junction formation by novel process sequence for PMOSFET

Method for forming a strained channel in a semiconductor device

Method for forming n and p wells in a semiconductor substrate using a single masking step

Formation of a thin oxide protection layer at poly sidewall and area surface

Forming silicides with reduced tailing on silicon germanium and silicon