Inventor

BURR GEOFFREY

US21 patents

⚠️ This page may combine multiple inventors who share the name “BURR GEOFFREY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BURR GEOFFREY

IBM

Analog-to-digital conversion with reconfigurable function mapping for neural networks activation function acceleration

Memory cell in wafer backside

Two-dimensional mesh for compute-in-memory accelerator architecture

Buried metal signal rail for memory arrays

Split pulse width modulation to reduce crossbar array integration time

Efficient tile mapping for row-by-row convolutional neural network mapping for analog artificial intelligence network inference

Selective application of multiple pulse durations to crossbar arrays

Efficient tile mapping for row-by-row convolutional neural network mapping for analog artificial intelligence network inference

Digital compute hardware for efficient element-wise and cross-vector maximum operations

Efficient data layout and alignment for wide-vector accelerator systems

Mitigation of conductance drift in neural network resistive processing units

Suppressing outlier drift coefficients while programming phase change memory synapses

Neuron-centric local learning rate for artificial neural networks to increase performance, learning rate margin, and reduce power consumption

Distributing device array currents across segment mirrors

Implicit vector concatenation within 2D mesh routing

Special-purpose digital-compute hardware for efficient element-wise aggregation, scaling and offset

Array-integrated upstream/downstream router for circuit switched parallel connectivity

Row-by-row convolutional neural network mapping for analog artificial intelligence network training

Closed loop programming of phase-change memory

Efficient processing of convolutional neural network layers using analog-memory-based hardware

INT BUSINESS MACHINES CORPORATION

Stochastic bitstream generation with in-situ function mapping