Inventor

HOSOKAWA KOHJI

JP40 patents

⚠️ This page may combine multiple inventors who share the name “HOSOKAWA KOHJI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HOSOKAWA KOHJI

IBM

DRAM with multiple virtual bank architecture for random row access

Encryption engine with an undetectable/tamper-proof private key in late node CMOS technology

Intra-unit column address increment system for memory

Single ended read write drive for memory

Neuron peripheral circuits for neuromorphic synaptic memory array based on neuron models

Memory cell structure

Communicating postsynaptic neuron fires to neuromorphic cores

Monitoring potential of neuron circuits

Monitoring potential of neuron circuits

Neuron peripheral circuits for neuromorphic synaptic memory array based on neuron models

Memory cell in wafer backside

Linearly weight updatable CMOS synaptic array without cell location dependence

Dynamic semiconductor storage device

Shared PMOS sense amplifier

Buried metal signal rail for memory arrays

Duty compensation scheme

Synapse memory

Synapse memory

On-chip Poisson spike generation

Encryption engine with an undetectable/tamper-proof private key in late node CMOS technology

Weight shifting for neuromorphic synapse array

Encryption engine with an undetectable/tamper proof private key in late node CMOS technology

Digitial STDP synapse and LIF neuron-based neuromorphic system

Digital STDP synapse and LIF neuron-based neuromorphic system

DRAM circuit and its operation method

DRAM circuit and its operation method

Neuromorphic chip for updating precise synaptic weight values

Memory cell structure

Memory cell structure

DRAM circuit and method of controlling the same

Implicit vector concatenation within 2D mesh routing

Performance and area efficient synapse memory cell structure

Linearly weight updatable CMOS synaptic array without cell location dependence

Circuit and method for detecting defects in semiconductor memory

LUT based neuron membrane potential update scheme in STDP neuromorphic systems

SAMSUNG ELECTRONICS CO LTD

LUT based synapse weight update scheme in STDP neuromorphic systems

Monitoring potential of neuron circuits

Timing sequence for digital STDP synapse and LIF neuron-based neuromorphic system

Neuron peripheral circuits for neuromorphic synaptic memory array based on neuron models

INFINEON TECHNOLOGIES AG

Power controlled input receiver