P

Inventor

STEPHENSON ROBERT JOHN

GB44 patents
⚠️ This page may combine multiple inventors who share the name “STEPHENSON ROBERT JOHN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ATOMERA INC

22 patents
US10109479B1Oct 23, 2018

Method of making a semiconductor device with a buried insulating layer formed by annealing a superlattice

ATOMERA INC82 citations98
US10566191B1Feb 18, 2020

Semiconductor device including superlattice structures with reduced defect densities

ATOMERA INC51 citations95
US10884185B2Jan 5, 2021

Semiconductor device including vertically integrated optical and electronic devices and comprising a superlattice

ATOMERA INC19 citations94
US10811498B2Oct 20, 2020

Method for making superlattice structures with reduced defect densities

ATOMERA INC35 citations94
US10763370B2Sep 1, 2020

Inverted T channel field effect transistor (ITFET) including a superlattice

ATOMERA INC30 citations94
US10741436B2Aug 11, 2020

Method for making a semiconductor device including non-monocrystalline stringer adjacent a superlattice-sti interface

ATOMERA INC30 citations94
US10727049B2Jul 28, 2020

Method for making a semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlattice

ATOMERA INC30 citations94
US10468245B2Nov 5, 2019

Semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlattice

ATOMERA INC46 citations94
US11387325B2Jul 12, 2022

Vertical semiconductor device with enhanced contact structure and associated methods

ATOMERA INC12 citations93
US11075078B1Jul 27, 2021

Method for making a semiconductor device including a superlattice within a recessed etch

ATOMERA INC21 citations93
US10879356B2Dec 29, 2020

Method for making a semiconductor device including enhanced contact structures having a superlattice

ATOMERA INC21 citations93
US10777451B2Sep 15, 2020

Semiconductor device including enhanced contact structures having a superlattice

ATOMERA INC30 citations93
US11978771B2May 7, 2024

Gate-all-around (GAA) device including a superlattice

ATOMERA INC7 citations86
US11848356B2Dec 19, 2023

Method for making semiconductor device including superlattice with oxygen and carbon monolayers

ATOMERA INC6 citations86
US11837634B2Dec 5, 2023

Semiconductor device including superlattice with oxygen and carbon monolayers

ATOMERA INC10 citations86
US11664459B2May 30, 2023

Method for making an inverted T channel field effect transistor (ITFET) including a superlattice

ATOMERA INC7 citations86
US11430869B2Aug 30, 2022

Method for making superlattice structures with reduced defect densities

ATOMERA INC8 citations86
US11355667B2Jun 7, 2022

Method for making semiconductor device including vertically integrated optical and electronic devices and comprising a superlattice

ATOMERA INC11 citations86
US11664427B2May 30, 2023

Vertical semiconductor device with enhanced contact structure and associated methods

ATOMERA INC7 citations85
US9721790B2Aug 1, 2017

Method for making enhanced semiconductor structures in single wafer processing chamber with desired uniformity control

ATOMERA INC11 citations84
US12142641B2Nov 12, 2024

Method for making gate-all-around (GAA) device including a superlattice

ATOMERA INC0 citations63
US12119380B2Oct 15, 2024

Method for making semiconductor device including superlattice with oxygen and carbon monolayers

ATOMERA INC0 citations63

MEARS TECHNOLOGIES INC

8 patents

RJ MEARS LLC

7 patents

MUDDY RIVER TECH INC

3 patents

MEARS ROBERT J

1 patent

CHEMTECH ANALYSIS INC

1 patent

PARADIGM ENV TECH INC

1 patent

PARADIGM ENVIRONMENTAL TECHNOLOGIES INC

1 patent