Inventor · disambiguated record
Vaughn Betz
Also filed as: BETZ VAUGHN · BETZ VAUGHN T · BETZ VAUGHN TIMOTHY
103 granted patents·7 pending applications·1,384 citations·filing 1995–2020
99Inventor score
Top patents by PatentIndex Score
110 records- 0196US7328377B1Error correction for programmable logic integrated circuitsALTERA CORP·Filed 2004·Granted Feb 5, 2008·126 cites·30 claims
- 0295US7555741B1Computer-aided-design tools for reducing power consumption in programmable logic devicesALTERA CORP·Filed 2006·Granted Jun 30, 2009·50 cites·23 claims
- 0395US6828824B2Heterogeneous interconnection architecture for programmable logic devicesALTERA TORONTO CO·Filed 2003·Granted Dec 7, 2004·68 cites·18 claims
- 0494US7129745B2Apparatus and methods for adjusting performance of integrated circuitsALTERA CORP·Filed 2004·Granted Oct 31, 2006·79 cites·9 claims
- 0593US8138786B2Apparatus and methods for adjusting performance of integrated circuitsLEWIS DAVID·Filed 2009·Granted Mar 20, 2012·17 cites·12 claims
- 0692US6763506B1Method of optimizing the design of electronic systems having multiple timing constraintsALTERA CORP·Filed 2001·Granted Jul 13, 2004·84 cites·52 claims
- 0791US7573317B2Apparatus and methods for adjusting performance of integrated circuitsALTERA CORP·Filed 2006·Granted Aug 11, 2009·16 cites·28 claims
- 0891US7218133B2Versatile logic element and logic array blockALTERA CORP·Filed 2005·Granted May 15, 2007·16 cites·6 claims
- 0990US8112678B1Error correction for programmable logic integrated circuitsLEWIS DAVID·Filed 2007·Granted Feb 7, 2012·21 cites·23 claims
- 1090US7061268B1Initializing a carry chain in a programmable logic deviceALTERA CORP·Filed 2004·Granted Jun 13, 2006·40 cites·27 claims
- 1190US6605962B2PLD architecture for flexible placement of IP function blocksALTERA CORP·Filed 2002·Granted Aug 12, 2003·27 cites·20 claims
- 1289US8095906B2Method and apparatus for performing parallel routing using a multi-threaded routing procedureBETZ VAUGHN·Filed 2008·Granted Jan 10, 2012·14 cites·36 claims
- 1389US7400167B2Apparatus and methods for optimizing the performance of programmable logic devicesALTERA CORP·Filed 2005·Granted Jul 15, 2008·17 cites·24 claims
- 1488US7877710B1Method and apparatus for deriving signal activities for power analysis and optimizationALTERA CORP·Filed 2006·Granted Jan 25, 2011·14 cites·29 claims
- 1588US7594208B1Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usageALTERA CORP·Filed 2006·Granted Sep 22, 2009·18 cites·31 claims
- 1688US7405589B2Apparatus and methods for power management in integrated circuitsALTERA CORP·Filed 2005·Granted Jul 29, 2008·13 cites·23 claims
- 1788US7051313B1Automatic generation of programmable logic device architecturesALTERA TORONTO CO·Filed 2003·Granted May 23, 2006·47 cites·34 claims
- 1888US6937064B1Versatile logic element and logic array blockALTERA CORP·Filed 2002·Granted Aug 30, 2005·26 cites·42 claims
- 1987US7853911B1Method and apparatus for performing path-level skew optimization and analysis for a logic designALTERA CORP·Filed 2005·Granted Dec 14, 2010·15 cites·36 claims
- 2086US8201129B2PLD architecture for flexible placement of IP function blocksLEE ANDY L·Filed 2009·Granted Jun 12, 2012·8 cites·30 claims
- 2186US7911240B1Clock switch-over circuits and methodsALTERA CORP·Filed 2007·Granted Mar 22, 2011·14 cites·22 claims
- 2286US7737751B1Periphery clock distribution network for a programmable logic deviceALTERA CORP·Filed 2007·Granted Jun 15, 2010·16 cites·44 claims
- 2386US7412680B1Method and apparatus for performing integrated global routing and buffer insertionALTERA CORP·Filed 2005·Granted Aug 12, 2008·16 cites·21 claims
- 2485US8296709B2Method and apparatus for performing parallel routing using a multi-threaded routing procedureBETZ VAUGHN·Filed 2011·Granted Oct 23, 2012·5 cites·23 claims
- 2585US8103975B2Apparatus and methods for optimizing the performance of programmable logic devices using multiple supply voltageLEWIS DAVID·Filed 2008·Granted Jan 24, 2012·10 cites·9 claims
- 2684US11755810B2Method and apparatus for performing parallel routing using a multi-threaded routing procedureALTERA CORP·Filed 2020·Granted Sep 12, 2023·1 cites·20 claims
- 2784US7138844B2Variable delay circuitryALTERA CORP·Filed 2005·Granted Nov 21, 2006·13 cites·21 claims
- 2883US8589849B1Method and apparatus for implementing soft constraints in tools used for designing programmable logic devicesBORER TERRY·Filed 2007·Granted Nov 19, 2013·10 cites·30 claims
- 2983US8533652B2Method and apparatus for performing parallel routing using a multi-threaded routing procedureBETZ VAUGHN·Filed 2012·Granted Sep 10, 2013·4 cites·25 claims
- 3082US7464362B1Method and apparatus for performing incremental compilationALTERA CORP·Filed 2006·Granted Dec 9, 2008·12 cites·17 claims
- 3182US7205791B1Bypass-able carry chain in a programmable logic deviceALTERA CORP·Filed 2004·Granted Apr 17, 2007·24 cites·25 claims
- 3282US7084665B1Distributed random access memory in a programmable logic deviceALTERA CORP·Filed 2004·Granted Aug 1, 2006·20 cites·33 claims
- 3382US6630842B1Routing architecture for a programmable logic deviceALTERA CORP·Filed 2002·Granted Oct 7, 2003·25 cites·75 claims
- 3481US8732639B1Method and apparatus for protecting, optimizing, and reporting synchronizersFUNG RYAN·Filed 2009·Granted May 20, 2014·9 cites·37 claims
- 3581US8572530B1Method and apparatus for performing path-level skew optimization and analysis for a logic designFUNG RYAN·Filed 2010·Granted Oct 29, 2013·5 cites·21 claims
- 3681US7188266B1Systems and methods for reducing static and total power consumption in a programmable logic deviceALTERA CORP·Filed 2004·Granted Mar 6, 2007·24 cites·50 claims
- 3781US6590419B1Heterogeneous interconnection architecture for programmable logic devicesALTERA TORONTO CO·Filed 1999·Granted Jul 8, 2003·35 cites·22 claims
- 3880US10242146B2Method and apparatus for placing and routing partial reconfiguration modulesALTERA CORP·Filed 2016·Granted Mar 26, 2019·2 cites·18 claims
- 3980US7861190B1Power-driven timing analysis and placement for programmable logicALTERA CORP·Filed 2005·Granted Dec 28, 2010·10 cites·27 claims
- 4079US9536034B2Method and apparatus for performing parallel routing using a multi-threaded routing procedureALTERA CORP·Filed 2014·Granted Jan 3, 2017·2 cites·23 claims
- 4179US7207020B1Method and apparatus for utilizing long-path and short-path timing constraints in an electronic-design-automation toolALTERA CORP·Filed 2004·Granted Apr 17, 2007·21 cites·49 claims
- 4278US9361421B2Method and apparatus for placing and routing partial reconfiguration modulesALTERA CORP·Filed 2014·Granted Jun 7, 2016·3 cites·19 claims
- 4378US9094014B2PLD architecture for flexible placement of IP function blocksALTERA CORP·Filed 2014·Granted Jul 28, 2015·2 cites·20 claims
- 4478US8935650B2Method and apparatus for performing parallel routing using a multi-threaded routing procedureALTERA CORP·Filed 2014·Granted Jan 13, 2015·2 cites·20 claims
- 4578US8739105B2Method and apparatus for performing parallel routing using a multi-threaded routing procedureALTERA CORP·Filed 2013·Granted May 27, 2014·2 cites·27 claims
- 4678US8732646B2PLD architecture for flexible placement of IP function blocksALTERA CORP·Filed 2013·Granted May 20, 2014·2 cites·20 claims
- 4777US8443325B1Method and apparatus for utilizing constraints for the routing of a design on a programmable logic deviceBETZ VAUGHN·Filed 2010·Granted May 14, 2013·3 cites·21 claims
- 4877US8250500B1Method and apparatus for deriving signal activities for power analysis and optimizationNETO DAVID·Filed 2006·Granted Aug 21, 2012·7 cites·16 claims
- 4977US8156355B2Systems and methods for reducing static and total power consumptionMENDEL DAVID·Filed 2008·Granted Apr 10, 2012·7 cites·21 claims
- 5077US7432734B2Versatile logic element and logic array blockALTERA CORP·Filed 2007·Granted Oct 7, 2008·6 cites·14 claims
Showing the top 50 of 110 patent records by PatentIndex Score.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →