Inventor

SUNG SEUNG HOON

US156 patents

⚠️ This page may combine multiple inventors who share the name “SUNG SEUNG HOON”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SUNG SEUNG HOON

INTEL CORP

Thin film transistors having U-shaped features

Source/drain diffusion barrier for germanium NMOS transistors

Transistor structures with a metal oxide contact buffer

Wurtzite heteroepitaxial structures with inclined sidewall facets for defect propagation control in silicon CMOS-compatible semiconductor devices

III-N epitaxial device structures on free standing silicon mesas

Group III-N transistor on nanoscale template structures

N-channel gallium nitride transistors

Variable gate width for gate all-around transistors

Deep gate-all-around semiconductor device having germanium or group III-V active layer

Nonplanar III-N transistors with compositionally graded semiconductor channels

Group III-N transistors on nanoscale template structures

Low sheet resistance GaN channel on Si substrates using InAlN and AlGaN bi-layer capping stack

Nonplanar III-N transistors with compositionally graded semiconductor channels

Group III-N transistors on nanoscale template structures

Source contact and channel interface to reduce body charging from band-to-band tunneling

Self-aligned structures and methods for asymmetric GaN transistors and enhancement mode operation

Forksheet transistors with dielectric or conductive spine

Stacked forksheet transistors

Transistor structures with a metal oxide contact buffer and a method of fabricating the transistor structures

Structures and methods for memory cells

Vertical thin-film transistors between metal layers

Contact electrodes and dielectric structures for thin film transistors

Relaxor ferroelectric capacitors and methods of fabrication

Stacked thin film transistors with nanowires

Vertical switching device with self-aligned contact

Wurtzite heteroepitaxial structures with inclined sidewall facets for defect propagation control in silicon CMOS-compatible semiconductor devices

Nanowire transistors with embedded dielectric spacers

Transistor gate trench engineering to decrease capacitance and resistance

Semiconductor devices with raised doped crystalline structures

Co-integrated III-N voltage regulator and RF power amplifier for envelope tracking systems

Integration of III-V devices on Si wafers

Thin film transistor with gate stack on multiple sides

Co-planar p-channel and n-channel gallium nitride-based transistors on silicon and techniques for forming same

Nanowire transistor fabrication with hardmask layers

Wide band gap transistor on non-native semiconductor substrate

Integrated circuit die having reduced defect group III-nitride layer and methods associated therewith

Methods and structures to prevent sidewall defects during selective epitaxy

Integration of III-V devices on Si wafers

III-N transistors with enhanced breakdown voltage

PILLARISETTY RAVI

Trench confined epitaxially grown device layer(s)

Trench confined epitaxially grown device layer(s)

Deep gate-all-around semiconductor device having germanium or group III-V active layer

Deep gate-all-around semiconductor device having germanium or group III-V active layer

THEN HAN WUI

Nonplanar III-N transistors with compositionally graded semiconductor channels

Group III-N transistors on nanoscale template structures

Group III-N transistors on nanoscale template structures

RACHMADY WILLY

Variable gate width for gate all-around transistors

PARK JIN-BAE

Time-frequency domain reflectometry apparatus and method

EDEN J GARY

Ellipsoidal microcavity plasma devices and powder blasting formation

GOEL NITI

Epitaxial film growth on patterned substrate