Inventor

RADOSAVLJEVIC MARKO

US384 patents

⚠️ This page may combine multiple inventors who share the name “RADOSAVLJEVIC MARKO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RADOSAVLJEVIC MARKO

INTEL CORP

Carbon nanotube energy well (CNEW) field effect transistor

Block contact architectures for nanoscale channel transistors

Block contact architectures for nanoscale channel transistors

Method for fabricating transistor with thinned channel

Quantum well MOSFET channels having uni-axial strain caused by metal source/drains, and conformal regrowth source/drains

Selective high-k dielectric film deposition for semiconductor device

Quantum well MOSFET channels having uni-axial strain caused by metal source/drains, and conformal regrowth source/drains

Apparatus and methods for forming a modulation doped non-planar transistor

Field effect transistor with metal source/drain regions

Group III-nitride (III-N) devices with reduced contact resistance and their methods of fabrication

Light-emitting diode (LED) and micro LED substrates and methods for making the same

Ferroelectric-based field-effect transistor with threshold voltage switching for enhanced on-state and off-state performance

Transition metal dichalcogenides (TMDCS) over III-nitride heteroepitaxial layers

Group III-N nanowire transistors

Wurtzite heteroepitaxial structures with inclined sidewall facets for defect propagation control in silicon CMOS-compatible semiconductor devices

III-N epitaxial device structures on free standing silicon mesas

Group III-N nanowire transistors

Aspect ratio trapping (ART) for fabricating vertical semiconductor devices

Group III-N transistor on nanoscale template structures

Quantum well MOSFET channels having lattice mismatch with metal source/drains, and conformal regrowth source/drains

N-channel gallium nitride transistors

Deep gate-all-around semiconductor device having germanium or group III-V active layer

Forming LED structures on silicon fins

Nonplanar III-N transistors with compositionally graded semiconductor channels

III-N material structure for gate-recessed transistors

Group III-N transistors on nanoscale template structures

CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture

Low sheet resistance GaN channel on Si substrates using InAlN and AlGaN bi-layer capping stack

Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation

III-N material structure for gate-recessed transistors

Group III-N nanowire transistors

Lattice mismatched hetero-epitaxial film

PILLARISETTY RAVI

Trench confined epitaxially grown device layer(s)

Non-planar germanium quantum well devices

Trench confined epitaxially grown device layer(s)

Contact techniques and configurations for reducing parasitic resistance in nanowire transistors

Non-planar germanium quantum well devices

THEN HAN WUI

Group III-N nanowire transistors

High voltage field effect transistors

Nonplanar III-N transistors with compositionally graded semiconductor channels

Group III-N transistors on nanoscale template structures

Non-planar III-N transistor

RADOSAVLJEVIC MARKO

CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture

Conductivity improvements for III-V semiconductor devices

Non-planar semiconductor device having channel region with low band-gap cladding layer

DEWEY GILBERT

Non-planar III-V field effect transistors with conformal metal gate electrode and nitrogen doping of gate dielectric interface

Non-planar semiconductor device having group III-V material active region with multi-dielectric gate stack

MAJHI PRASHANT

Quantum well MOSFET channels having uni-axial strain caused by metal source/drains, and conformal regrowth source/drains

UNIV PENNSYLVANIA

Fabrication of nanometer size gaps on an electrode

IBM

Catalyst-free growth of single-wall carbon nanotubes