Inventor

RAGHUNATHAN ANAND

US35 patents

⚠️ This page may combine multiple inventors who share the name “RAGHUNATHAN ANAND”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RAGHUNATHAN ANAND

NEC CORP

Verification of scheduling in the presence of loops using uninterpreted symbolic simulation

Verification of scheduling in the presence of loops using uninterpreted symbolic simulation

Power mode based macro-models for power estimation of electronic circuits

Method for synthesis of common-case optimized circuits to improve performance and power dissipation

High performance communication architecture for circuit designs using probabilistic allocation of resources

Flexible crossbar switching fabric

System for the design of high-performance communication architecture for system-on-chips using communication architecture tuners

PURDUE RESEARCH FOUNDATION

System and method for in-memory computing

Ternary in-memory accelerator

Ternary in-memory accelerator

Approximate cache memory

Approximate cache memory

Tomographic reconstruction system

NEC USA INC

Method and apparatus for efficient register-transfer level (RTL) power estimation

Constrained register sharing technique for low power VLSI design

Method for verification of RTL generated from scheduled behavior in a high-level synthesis flow

Controller-based power management for low-power sequential circuits

Process for dynamic composition and test cycles reduction

Common case optimized circuit structure for high-performance and low-power VLSI designs

NEC LAB AMERICA INC

System-level test architecture for delivery of compressed tests

Voice-based multimodal speaker authentication using adaptive training and applications thereof

Automatic pipelining framework for heterogeneous parallel computing systems

Power estimation employing cycle-accurate functional descriptions

UNIV PRINCETON

Design tools for high-level synthesis of a low-power data path

Vibration-based secure side channel for medical devices

CHAKRADHAR SRIMAT

Systems and methods for implementing best-effort parallel computing frameworks

Cross-layer system architecture design

INTEL CORP

Apparatuses, methods, and systems for access synchronization in a shared memory

Apparatuses, methods, and systems for access synchronization in a shared memory

NIPPON ELECTRIC CO

Register transfer level power optimization with emphasis on glitch analysis and reduction

JHA NIRAJ K

Securing medical devices through wireless monitoring and anomaly detection

CHAKRADHAR SRIMAT T

Methods and systems for managing computations on a hybrid computing platform including a parallel accelerator

NEC ELECTRONICS INC

Multi-level power macromodeling

UNIV CALIFORNIA

Methodology for the design of high-performance communication architectures for system-on-chips using communication architecture tuners

Mosenia Arsalan

Continuous authentication system and method based on BioAura