Inventor

SOREFF JEFFREY P

US15 patents

⚠️ This page may combine multiple inventors who share the name “SOREFF JEFFREY P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

10 patents

US5365463ANov 15, 1994

Method for evaluating the timing of digital machines with statistical variability in their delays

IBM73 citations93

US6763504B2Jul 13, 2004

Method for reducing RC parasitics in interconnect networks of an integrated circuit

IBM20 citations87

US6718523B2Apr 6, 2004

Reduced pessimism clock gating tests for a timing analysis tool

IBM15 citations82

US7325210B2Jan 29, 2008

Hybrid linear wire model approach to tuning transistor widths of circuits with RC interconnect

IBM17 citations81

US7225419B2May 29, 2007

FOREMAN ERIC A

2 patents

US8141014B2Mar 20, 2012

System and method for common history pessimism relief during static timing analysis

FOREMAN ERIC A12 citations83

US8108816B2Jan 31, 2012

Device history based delay variation adjustment during static timing analysis

FOREMAN ERIC A7 citations83

SOREFF JEFFREY P

2 patents

US8607176B2Dec 10, 2013

Delay model construction in the presence of multiple input switching events

SOREFF JEFFREY P5 citations65

US8201120B2Jun 12, 2012

Timing point selection for a static timing analysis in the presence of interconnect electrical elements

SOREFF JEFFREY P4 citations56

HATHAWAY DAVID J

1 patent

US8655634B2Feb 18, 2014

Modeling loading effects of a transistor network

HATHAWAY DAVID J1 citations47

SOREFF JEFFREY P

IBM

Method for evaluating the timing of digital machines with statistical variability in their delays

Method for reducing RC parasitics in interconnect networks of an integrated circuit

Reduced pessimism clock gating tests for a timing analysis tool

Hybrid linear wire model approach to tuning transistor widths of circuits with RC interconnect

Methods for modeling latch transparency

Model order reduction in transistor level timing

Model order reduction in transistor level timing

Model order reduction in transistor level timing

Methods for modeling latch transparency

System and method for improved hierarchical analysis of electronic circuits

FOREMAN ERIC A

System and method for common history pessimism relief during static timing analysis

Device history based delay variation adjustment during static timing analysis

SOREFF JEFFREY P

Delay model construction in the presence of multiple input switching events

Timing point selection for a static timing analysis in the presence of interconnect electrical elements

HATHAWAY DAVID J

Modeling loading effects of a transistor network