Inventor
SRIVASTAVA SUDESH CHANDRA
IN4 patents
Patents
4 patentsUS9319045B1Apr 19, 2016
Method and apparatus for reducing gate leakage of low threshold transistors during low power mode in a multi-power-domain chip
TEXAS INSTRUMENTS INC3 citations68
US11631454B2Apr 18, 2023
Methods and apparatus for reduced area control register circuit
TEXAS INSTRUMENTS INC0 citations55
US9705481B1Jul 11, 2017
Area-optimized retention flop implementation
TEXAS INSTRUMENTS INC0 citations47
US10559351B2Feb 11, 2020
Methods and apparatus for reduced area control register circuit
TEXAS INSTRUMENTS INC0 citations45