Inventor
TAM SIMON M
US27 patents
Patents
27 patentsUS6908227B2Jun 21, 2005
Apparatus for thermal management of multiple core microprocessors
INTEL CORP151 citations99
US4780424AOct 25, 1988
Process for fabricating electrically alterable floating gate memory devices
INTEL CORP222 citations99
US6788156B2Sep 7, 2004
Adaptive variable frequency clock system for high performance low power microprocessors
INTEL CORP82 citations98
US6762629B2Jul 13, 2004
VCC adaptive dynamically variable frequency clock system for high performance low power microprocessors
INTEL CORP116 citations98
US7144152B2Dec 5, 2006
Apparatus for thermal management of multiple core microprocessors
INTEL CORP51 citations96
US6608528B2Aug 19, 2003
Adaptive variable frequency clock system for high performance low power microprocessors
INTEL CORP62 citations96
US6201448B1Mar 13, 2001
Method and apparatus to reduce clock jitter of an on-chip clock signal
INTEL CORP59 citations96
US6067656AMay 23, 2000
Method and apparatus for detecting soft errors in content addressable memory arrays
INTEL CORP85 citations96
US5268320ADec 7, 1993
Method of increasing the accuracy of an analog circuit employing floating gate memory devices
INTEL CORP67 citations96
US5264734ANov 23, 1993
Difference calculating neural network utilizing switched capacitors
INTEL CORP58 citations96
US5256911AOct 26, 1993
Neural network with multiplexed snyaptic processing
INTEL CORP94 citations96
US5146602ASep 8, 1992
Method of increasing the accuracy of an analog neural network and the like
INTEL CORP53 citations96
US4961002AOct 2, 1990
Synapse cell employing dual gate transistor structure
INTEL CORP84 citations96
US5055897AOct 8, 1991
Semiconductor cell for neural network and the like
INTEL CORP78 citations95
US4950917AAug 21, 1990
Semiconductor cell for neural network employing a four-quadrant multiplier
INTEL CORP73 citations95
US6172937B1Jan 9, 2001
Multiple synthesizer based timing signal generation scheme
INTEL CORP36 citations93
US5087826AFeb 11, 1992
Multi-layer neural network employing multiplexed output neurons
INTEL CORP38 citations92
US4956564ASep 11, 1990
Adaptive synapse cell providing both excitatory and inhibitory connections in an associative network
INTEL CORP52 citations92
US4949140AAug 14, 1990
EEPROM cell with integral select transistor
INTEL CORP38 citations92
US4814286AMar 21, 1989
EEPROM cell with integral select transistor
INTEL CORP34 citations92
US4797856AJan 10, 1989
Self-limiting erase scheme for EEPROM
INTEL CORP63 citations91
US4957877ASep 18, 1990
Process for simultaneously fabricating EEPROM cell and flash EPROM cell
INTEL CORP53 citations90
US7409568B2Aug 5, 2008
Power supply voltage droop compensated clock modulation for microprocessors
INTEL CORP21 citations88
US7225349B2May 29, 2007
Power supply voltage droop compensated clock modulation for microprocessors
INTEL CORP25 citations88
US5247606ASep 21, 1993
Adaptively setting analog weights in a neural network and the like
INTEL CORP16 citations74
US5075869ADec 24, 1991
Neural network exhibiting improved tolerance to temperature and power supply variations
INTEL CORP11 citations74
US4806202AFeb 21, 1989
Field enhanced tunnel oxide on treated substrates
INTEL CORP18 citations72