P

Inventor

KING STEVEN R

US41 patents
⚠️ This page may combine multiple inventors who share the name “KING STEVEN R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

24 patents
US8031606B2Oct 4, 2011

Packet switching

INTEL CORP95 citations97
US7958436B2Jun 7, 2011

Performing a cyclic redundancy checksum operation responsive to a user-level instruction

INTEL CORP13 citations92
US11048579B2Jun 29, 2021

Performing a cyclic redundancy checksum operation responsive to a user-level instruction

INTEL CORP3 citations84
US10379938B2Aug 13, 2019

Performing a cyclic redundancy checksum operation responsive to a user-level instruction

INTEL CORP4 citations84
US9645884B2May 9, 2017

Performing a cyclic redundancy checksum operation responsive to a user-level instruction

INTEL CORP5 citations84
US9116684B2Aug 25, 2015

Performing a cyclic redundancy checksum operation responsive to a user-level instruction

INTEL CORP4 citations84
US8769385B2Jul 1, 2014

Performing a cyclic redundancy checksum operation responsive to a user-level instruction

INTEL CORP4 citations84
US7925957B2Apr 12, 2011

Validating data using processor instructions

INTEL CORP14 citations83
US7523378B2Apr 21, 2009

Techniques to determine integrity of information

INTEL CORP12 citations82
US8856627B2Oct 7, 2014

Performing a cyclic redundancy checksum operation responsive to a user-level instruction

INTEL CORP3 citations74
US8793559B2Jul 29, 2014

Performing a cyclic redundancy checksum operation responsive to a user-level instruction

INTEL CORP3 citations74
US8775910B2Jul 8, 2014

Performing a cyclic redundancy checksum operation responsive to a user-level instruction

INTEL CORP3 citations74
US8775912B2Jul 8, 2014

Performing a cyclic redundancy checksum operation responsive to a user-level instruction

INTEL CORP3 citations74
US8775911B2Jul 8, 2014

Performing a cyclic redundancy checksum operation responsive to a user-level instruction

INTEL CORP3 citations74
US8769386B2Jul 1, 2014

Performing a cyclic redundancy checksum operation responsive to a user-level instruction

INTEL CORP3 citations74
US11899530B2Feb 13, 2024

Performing a cyclic redundancy checksum operation responsive to a user-level instruction

INTEL CORP0 citations73
US9674097B2Jun 6, 2017

Packet switching

INTEL CORP2 citations72
US9262159B2Feb 16, 2016

Performing a cyclic redundancy checksum operation responsive to a user-level instruction

INTEL CORP2 citations68
US7631115B2Dec 8, 2009

Techniques to manage data transfer utilizing buffer hints included in memory access requests

INTEL CORP2 citations63
US7573895B2Aug 11, 2009

Software assisted RDMA

INTEL CORP5 citations63
US8934344B2Jan 13, 2015

Packet switching

INTEL CORP3 citations61
US10447604B2Oct 15, 2019

Packet switching

INTEL CORP0 citations51
US7433975B2Oct 7, 2008

Integrated circuit capable of marker stripping

INTEL CORP0 citations50
US7443848B2Oct 28, 2008

External device-based prefetching mechanism

INTEL CORP0 citations42

KING STEVEN R

5 patents

GAS RES INST

3 patents

WOODWARD GOVERNOR CO

3 patents

SOUTHWEST RES INST

2 patents

ECONTROLS INC

1 patent

MESA ENVIRONMENTAL VENTURES LI

1 patent

MEMON MAZHAR I

1 patent

SHAMAN PHARMACEUTICALS INC

1 patent