Inventor

LUR WATER

TW184 patents

⚠️ This page may combine multiple inventors who share the name “LUR WATER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LUR WATER

UNITED MICROELECTRONICS CORP

Method of gap filling

Dual damascene process

Air gap for dual damascene applications

Air gap formation method for reducing undesired capacitive coupling between interconnects in an integrated circuit device

Air gap for tungsten/aluminum plug applications

Copper damascene technology for ultra large scale integration circuits

Multi-step high density plasma chemical vapor deposition process

Method of preventing fluorine-induced gate oxide degradation in WSix polycide structure

Method for manufacturing dielectric layer

Method for fabricating shallow trench isolation structure

Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit

Method of manufacturing copper interconnect

Chemical mechanical polishing for forming a shallow trench isolation structure

Apparatus for controlling uniformity of polished material

One step salicide process without bridging

Method of fabricating a shallow-trench isolation structure in integrated circuit

Method for fabricating a shallow-trench isolation structure with a rounded corner in integrated circuit

Method for growing hemispherical grain silicon

Prevention of fluorine-induced gate oxide degradation in WSi polycide structure

Metal layout pattern for improved passivation layer coverage

Method to solve holes in passivation by metal layout

Silicon-on-insulator technique with buried gap

VLSI device with global planarization

Multi-level conductor process in VLSI fabrication utilizing an air bridge

Stress-free isolation layer

Self-aligned trenched contact (satc) process

High density plasma chemical vapor deposition process

Method of fabricating dual damascene

Stress relaxation in dielectric before metallization

Field oxide with curvilinear boundaries and method of producing the same

Method of forming device isolation regions

Trench isolation for both large and small areas by means of silicon nodules after metal etching

Chemical mechanical polishing for forming a shallow trench isolation structure

Method for improving non-uniformity of chemical mechanical polishing by over coating

Method of fabricating dual damascene structure

Method for forming dielectric layers

Method for forming an inter-metal dielectric layer

Method of improving surface planarity of chemical-mechanical polishing operation by forming shallow dummy pattern

Method of designing active region pattern with shift dummy pattern

Method of fabricating a dual damascene structure in an integrated circuit

Method of fabricating gate

Method of fabricating a glue layer of contact/via

Method of fabricating a dynamic random access memory device

Physical vapor deposition device for forming a uniform metal layer on a semiconductor wafer

Method for forming polysilicon gate

Fabricating method of a barrier layer

Method of manufacturing embedded dynamic random access memory

UNITED MICROELECTRONICS

Method for forming shallow trench isolation

UNITED MICORELECTRONICS CORP

Air gap structure and formation method for reducing undesired capacitive coupling between interconnects in an integrated circuit device

(unassigned)

Method for unlanded via etching using etch stop