Inventor

NORWOOD ROGER D

US27 patents

⚠️ This page may combine multiple inventors who share the name “NORWOOD ROGER D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NORWOOD ROGER D

TEXAS INSTRUMENTS INC

System including a data processor, a synchronous dram, a peripheral device, and a system clock

Method and apparatus for inhibiting a predecoder when selecting a redundant row line

Random access memory arranged for operating synchronously with a microprocessor and a system including a data processor, a synchronous DRAM, a peripheral device, and a system clock

High speed, low-power nibble mode circuitry for dynamic memory

Clock skew circuit

Interface level programmability

Method and apparatus for inhibiting a predecoder when selecting a redundant row line

Power-up pulse generator circuit

Glitch suppression circuit

Semiconductor dynamic memory device with multiplexed sense amplifier and write-activated active loads

Data processing system arranged for operating synchronously with a high speed memory

Random access memory with latency arranged for operating synchronously with a micro processor and a system including a data processor, a synchronous DRAM, a peripheral device, and a system clock

Memory access circuits for test time reduction

High-speed memory arranged for operating synchronously with a microprocessor

High speed memory arranged for operating synchronously with a microprocessor

Method for generating power-up pulse

Semiconductor dynamic memory device with decoded active loads

Semiconductor dynamic memory device with metal-level selection of page mode or nibble mode

Dual receiver edge-triggered digital signal level detection system

Distributed signal transmission to an integrated circuit array

Integrated circuit furnishing a segmented input circuit

MICRON TECHNOLOGY INC

Asynchronous interface circuit and method for a pseudo-static memory device

Apparatuses and methods for address detection

Multiplexed noisy-quiet power busing for improved area efficiencies and pause performance in DRAM memories

Asynchronous interface circuit and method for a pseudo-static memory device

Apparatuses and methods for address detection

REDDY CHITRANJAN N

Boot-strapped decoder circuit