Inventor

HSIEH CHANG-MING

US34 patents

⚠️ This page may combine multiple inventors who share the name “HSIEH CHANG-MING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HSIEH CHANG-MING

IBM

High-density DRAM structure on soi

Method of making a high-density DRAM structure on SOI

Methods to enhance SOI SRAM cell stability

SOI transistor having a self-aligned body contact

Method of forming a SOI transistor having a self-aligned body contact

Flash EEPROM

Flash EEPROM with dual-sidewall gate

Bonded wafer structure having a buried insulation layer

Thermal dissipation of integrated circuits using diamond paths

Bonded wafer structure having a buried insulation layer

Method of making a vertical gate transistor with low temperature epitaxial channel

Vertical gate transistor with low temperature epitaxial channel

SOI transistor having a self-aligned body contact

Modular MOSFETS for high aspect ratio applications

Method to suppress subthreshold leakage due to sharp isolation corners in submicron FET structures

Advanced silicon on oxide semiconductor device structure for BiCMOS integrated circuit

Method of forming silicon on oxide semiconductor device structure for BiCMOS integrated circuits

Method of forming integrated interconnect for very high density DRAMs

Transistor structure utilizing a deposited epitaxial base region

Gate controlled Schottky barrier diode

Vertical bipolar transistor with recessed epitaxially grown intrinsic base region

Vertical bipolar transistor with recessed epitaxially grown intrinsic base region

Method of making a lateral transistor

Method to suppress subthreshold leakage due to sharp isolation corners in submicron FET structures

Field effect transistor formed with deep-submicron gate

Vertical-gate CMOS compatible lateral bipolar transistor

Method of making trimmable modular MOSFETs for high aspect ratio applications

Lateral transistor and method of making same

Method of forming a novel vertical-gate CMOS compatible lateral bipolar transistor

Method of forming a doped region in a semiconductor substrate utilizing a sacrificial epitaxial silicon layer

Novel vertical-gate CMOS compatible lateral bipolar transistor

Lateral PNP transistor and method for forming same

Method for forming lateral PNP transistor

COOK ROBERT K

Method for forming a complementary bipolar transistor structure including a self-aligned vertical PNP transistor