Inventor

HSU LOUIS L C

US39 patents

⚠️ This page may combine multiple inventors who share the name “HSU LOUIS L C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HSU LOUIS L C

IBM

Fuse processing using dielectric planarization pillars

High-density DRAM structure on soi

Method of making a high-density DRAM structure on SOI

Word line driver for dynamic random access memories

Charge pump system having multiple charging rates and corresponding method

Charge pump system having multiple independently activated charge pumps and corresponding method

MOS transistors structure for reducing the size of pitch limited circuits

Programmable/reprogrammable fuse

Semiconductor device and wafer structure having a planar buried interconnect by wafer bonding

CMOS transistor with two-layer inverse-T tungsten gate

High density planar magnetic domain wall memory apparatus

Structure for stochastic integrated circuit personalization

Method of forming high density planar magnetic domain wall memory

Write operations for phase-change-material memory

Non-volatile content addressable memory using phase-change-material memory elements

Method of making a vertical gate transistor with low temperature epitaxial channel

Vertical gate transistor with low temperature epitaxial channel

Diamond as a polish-stop layer for chemical-mechanical planarization in a damascene process flow

Auto-programmable current limiter to control current leakage due to bitline to wordline short

Method for fabricating a MOS transistor with two-layer inverse-T tungsten gate structure

Advanced silicon on oxide semiconductor device structure for BiCMOS integrated circuit

Method of forming silicon on oxide semiconductor device structure for BiCMOS integrated circuits

Dual phase and hybrid phase shifting mask fabrication using a surface etch monitoring technique

High density planar magnetic domain wall memory apparatus

Write operations for phase-change-material memory

Addressable hierarchical metal wire test methodology

Method and structure for forming slot via bitline for MRAM devices

Semiconductor constructions and semiconductor device fabrication methods

Semiconductor constructions and semiconductor device fabrication methods

Semiconductor device with diamond-like carbon layer as a polish-stop layer

Method for forming slot via bitline for MRAM devices

Structure and method for stochastic integrated circuit personalization

Novel vertical-gate CMOS compatible lateral bipolar transistor

Universal clock generator circuit and adjustment method for providing a plurality of clock frequencies

Self-repair integrated circuit and repair method

SIEMENS AG

Reduced parasitic leakage in semiconductor devices

Reduced parasitic leakage in semiconductor devices

HSU LOUIS L C

Self-repair integrated circuit and repair method

Self-repair integrated circuit and repair method