Inventor

OGURA SEIKI

US129 patents

⚠️ This page may combine multiple inventors who share the name “OGURA SEIKI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

OGURA SEIKI

HALO LSI INC

Twin NAND device structure, array operations and fabrication method

Twin insulator charge storage device operation and its fabrication method

Fast program to program verify method

Simplified twin monos fabrication method with three extra masks to standard CMOS

Fast program to program verify method

Twin MONOS cell fabrication method and array organization

Array architecture and operation methods for a nonvolatile memory

Twin NAND device structure, array operations and fabrication method

Stitch and select implementation in twin MONOS array

Process for making and programming and operating a dual-bit multi-level ballistic flash memory

Twin MONOS array metal bit organization and single cell operation

Double sidewall short channel split gate flash memory

Data programming implementation for high efficiency CHE injection

Process for making and programming and operating a dual-bit multi-level ballistic flash memory

Twin MONOS memory cell usage for wide program

IBM

High-density DRAM structure on soi

Method of making a high-density DRAM structure on SOI

Method for removing protuberances at the surface of a semiconductor wafer using a chem-mech polishing technique

Method of preventing asymmetric etching of lines in sub-micrometer range sidewall images transfer

Isolation structure using liquid phase oxide deposition

Flash EEPROM

Flash EEPROM with dual-sidewall gate

Process for making and programming a flash memory array

Process for making and programming a flash memory array

Method of fabricating a semiconductor device with raised diffusions and isolation

Method for manufacturing a Bi-CMOS device

Method of fabricating an MOS dynamic RAM with lightly doped drain

Packing density for flash memories

Method of forming a BiCMOS SOI wafer having thin and thick SOI regions of silicon

GaAs short channel lightly doped drain MESFET structure and fabrication

HALO LSI DESIGN & DEVICE TECH

Nonvolatile memory cell, method of programming the same and nonvolatile memory array

Integration method for sidewall split gate monos transistor

Process for making and programming and operating a dual-bit multi-level ballistic flash memory

Low voltage EEPROM/NVRAM transistors and making method

Usage of word voltage assistance in twin MONOS cell during program and erase

Process for making and programming and operating a dual-bit multi-level ballistic MONOS memory

Double sidewall short channel split gate flash memory

Integration method for sidewall split gate flash transistor

Read reference scheme for flash memory

MATSUSHITA ELECTRIC INDUSTRIAL CO LTD

Nonvolatile semiconductor memory device and method for fabricating the same and semiconductor integrated circuit

Nonvolatile semiconductor device capable of increased electron injection efficiency

Nonvolatile semiconductor memory device and method for fabricating the same, and semiconductor integrated circuit device

Nonvolatile semiconductor memory device and method for fabricating the same, and semiconductor integrated circuit device

Semiconductor device and method for fabricating the same

Nonvolatile semiconductor memory device and method for fabricating the same and semiconductor integrated circuit

HALO LSI DEVICE & DESIGN TECHN

Nonvolatile memory cell, method of programming the same and nonvolatile memory array

Process for making and programming and operating a dual-bit multi-level ballistic flash memory

HALO INC

Twin MONOS cell fabrication method and array organization

NEW HALO INC

Dual-bit multi-level ballistic MONOS memory

HALO LSI DESIGN DEVICE TECHNOL

Low voltage EEPROM/NVRAM transistors and making method