Inventor
GARCIA SERAFIN E
US10 patents
Patents
10 patentsUS6694390B1Feb 17, 2004
Managing bus transaction dependencies
INTEL CORP118 citations97
US6584526B1Jun 24, 2003
Inserting bus inversion scheme in bus path without increased access latency
INTEL CORP84 citations97
US6433785B1Aug 13, 2002
Method and apparatus for improving processor to graphics device throughput
INTEL CORP91 citations96
US6516375B1Feb 4, 2003
Peripheral component interconnect (PCI) configuration emulation for hub interface
INTEL CORP30 citations92
US6983339B1Jan 3, 2006
Method and apparatus for processing interrupts of a bus
INTEL CORP49 citations91
US6782435B2Aug 24, 2004
Device for spatially and temporally reordering for data between a processor, memory and peripherals
INTEL CORP42 citations91
US6505259B1Jan 7, 2003
Reordering of burst data transfers across a host bridge
INTEL CORP15 citations89
US7082480B2Jul 25, 2006
Managing bus transaction dependencies
INTEL CORP3 citations62
US7058736B2Jun 6, 2006
Reordering of burst data transfers across a host bridge
INTEL CORP3 citations59
US7100032B2Aug 29, 2006
Method and apparatus for identifying hardware compatibility and enabling stable software images
INTEL CORP1 citations46