Inventor

PAPWORTH DAVID B

US56 patents

⚠️ This page may combine multiple inventors who share the name “PAPWORTH DAVID B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PAPWORTH DAVID B

INTEL CORP

Method for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder buffer

Linear address extension and mapping to physical memory using 4 and 8 byte page table entries in a 32-bit microprocessor

Processor that redirects an instruction fetch pipeline immediately upon detection of a mispredicted branch while committing prior instructions to an architectural state

Speculative and committed resource files in an out-of-order processor

Method and apparatus for resolving return from subroutine instructions in a computer processor

Method and apparatus for state recovery following branch misprediction in an out-of-order microprocessor

Method and apparatus for implementing a set-associative branch target buffer

Circuit and method for scheduling instructions by predicting future availability of resources required for execution

Dual prediction branch system having two step of branch recovery process which activated only when mispredicted branch is the oldest instruction in the out-of-order unit

Method and apparatus for dynamic allocation of multiple buffers in a processor

Mechanism for efficiently overlapping multiple operand types in a microprocessor

Method and apparatus for implementing a branch target buffer in CISC processor

Method and apparatus for changing flow of control in a processor

Method and apparatus for predicting and handling resolving return from subroutine instructions in a computer processor

Method and apparatus for predicting, clearing and redirecting unpredicted changes in instruction flow in a microprocessor

Method and apparatus for maintaining a macro instruction for refetching in a pipelined processor

Method and apparatus for signalling a store buffer to output buffered store data for a load operation on an out-of-order execution computer system

Methods and apparatus for determining memory operating characteristics for given memory locations via assigned address ranges

Idiom recognizer within a register alias table

Coordinating speculative and committed state register source data and immediate source data in a processor

Circuit and method for scheduling instructions by predicting future availability of resources required for execution

Entry allocation in a circular buffer using wrap bits indicating whether a queue of the circular buffer has been traversed

Apparatus and method for handling string operations in a pipelined processor

Method and apparatus for performing error correction on data from an external memory

Method and apparatus for pipeline streamlining where resources are immediate or certainly retired

Method and apparatus for maximum throughput scheduling of dependent operations in a pipelined processor

Exception handling in a processor that performs speculative out-of-order instruction execution

Register alias table update to indicate architecturally visible state

Computer system with self-consistent ordering mechanism

Method and apparatus for dispatching and executing a load operation to memory

Method and apparatus for zero extension and bit shifting to preserve register parameters in a microprocessor utilizing register renaming

Method and apparatus for avoiding writeback conflicts between execution units sharing a common writeback path

Methods and apparatus for fordwarding buffered store data on an out-of-order execution computer system

Hybrid execution unit for complex microprocessor

Method and apparatus for implementing a non-blocking translation lookaside buffer

Method and apparatus for zero extension and bit shifting to preserve register parameters in a microprocessor utilizing register renaming

Apparatus for pipeline streamlining where resources are immediate or certainly retired

Ready selection of data dependent instructions using multi-cycle cams in a processor performing out-of-order instruction execution

Method and apparatus for a branch instruction pointer table

Circuit and method for scheduling instructions by predicting future availability of resources required for execution

Method and apparatus for performing multiple load operations to the same memory location in a computer system

Method and apparatus for implementing a set-associative branch target buffer

PRIME COMPUTER INC

Data processing apparatus and method employing instruction flow prediction

Data processing apparatus and method employing collision detection and prediction

Memory access method and apparatus in multiple processor systems

DIGITAL EQUIPMENT CORP

Instruction storage and cache miss recovery in a high speed multiprocessing parallel processing apparatus

Instruction storage method with a compressed format using a mask word

MULTIFLOW COMPUTER INC

Hierarchical priority branch handling for parallel execution in a parallel processor

Virtual address table look aside buffer miss recovery method and apparatus

(unassigned)

Out-of-order processor with a memory subsystem which handles speculatively dispatched load operations